From tafuller at eng.ucsd.edu  Wed Mar  1 11:43:39 2023
From: tafuller at eng.ucsd.edu (Timothy Fuller)
Date: Wed, 1 Mar 2023 08:43:39 -0800
Subject: [labnetwork] Cryo-piping contractors for LN2 piping sought
In-Reply-To: <AC.4F.08004.C66BEF36@smtp02.aqua.bos.sync.lan>
References: <DM6PR11MB316257914858687CD6BC5570D7AC9@DM6PR11MB3162.namprd11.prod.outlook.com>
 <AC.4F.08004.C66BEF36@smtp02.aqua.bos.sync.lan>
Message-ID: <CANxZiKo0-R4kNsn2wh+q+NCTQ9XsVyweoZzeV7PMz0=zXKKYtA@mail.gmail.com>

When I worked at HRL our original installation had KF 25 Buna-N o-rings for
the vacuum jacket.  After replacing them with Viton o-rings, the vacuum
jacket was leak tight.

On Wed, Mar 1, 2023 at 4:45?AM johnboyle <johnboyle at fast.net> wrote:

> Check Acme Cryogenics, Allentown, PA. They make VIP, phase separators, do
> installation and repairs. Ask for Field Services
>
> John Boyle
>
>
>
> Sent from my Verizon, Samsung Galaxy smartphone
>
>
> -------- Original message --------
> From: "Collins, Deon" <deonc69 at illinois.edu>
> Date: 2/28/23 7:46 PM (GMT-05:00)
> To: "Metzler, Meredith G. (Fed)" <meredith.metzler at nist.gov>,
> labnetwork at mtl.mit.edu
> Subject: Re: [labnetwork] Cryo-piping contractors for LN2 piping sought
>
> Your vacuum jacket has failed. We are going through the same situation
> with our static LN2 delivery lines.
>
>
>
> Is your phase separator a Static or Dynamic system?
>
>
>
> *From:* labnetwork <labnetwork-bounces at mtl.mit.edu> * On Behalf Of *Metzler,
> Meredith G. (Fed)
> *Sent:* Tuesday, February 28, 2023 2:08 PM
> *To:* labnetwork at mtl.mit.edu
> *Subject:* [labnetwork] Cryo-piping contractors for LN2 piping sought
>
>
>
> We are hoping the community can assist us in identifying a vendor who can
> inspect an existing LN2 delivery piping system in the cleanroom for our
> cryo-etch tools. We've recently started experiencing issues with a phase
> separator that keeps building up a large block of ice on the outside of it.
>
>
>
> We have a 5 Gallon phase separator made by Chart Inc. with one outlet. It
> feeds liquid nitrogen to several tools in the etch bay of the cleanroom.
> The LN2 system is house regulated to 40 PSI at the inlet. The unit
> separates the gaseous N2 from the liquid. The liquid is stored in the 5
> gallon volume surrounded by a vacuum jacket to prevent icing. The final LN2
> inlet connection to the phase separator, the exhaust connection, and the
> over pressure relief connection seem to be the biggest points of failure.
> At these three points we have cold air and moisture condensation that forms
> an ice ball.
>
>
>
> Although, we have made many at wrapping and insulating these connection
> points, we cannot quite get the coverage to eliminate this ice ball.
>
>
>
> Does the community have any preferred cryo-piping contractors they can
> recommend to assist with solving this issue and any of our future
> cryo-piping needs?
>
>
>
> Thanks!
>
>
>
> Meredith Metzler
>
> National Institute of Standards and Technology, Physical Measurement
> Laboratory
>
> Process Engineer ? Center for Nanoscale Science and Technology Facility,
> NanoFab
>
> 100 Bureau Drive, Mail Stop 6201, Building 216
>
> Gaithersburg, MD 20899
>
> 301-975-8187
>
> meredith.metzler at nist.gov
>
> https://www.nist.gov/cnst
> <https://urldefense.com/v3/__https:/www.nist.gov/cnst__;!!DZ3fjg!-6Lfwk5cCgFK0WcjbkRqEZm2A8T7loqa2OV_9x-WW72ajmC1A4euSzW2VyRMpj0J8yR1_DdWvG0axt3nRQj-R1EmQJ2lypVZ$>
>
>
> _______________________________________________
> labnetwork mailing list
> labnetwork at mtl.mit.edu
> https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork
>
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From rand.haley at louisville.edu  Thu Mar  2 10:29:17 2023
From: rand.haley at louisville.edu (Haley, Rand)
Date: Thu, 2 Mar 2023 15:29:17 +0000
Subject: [labnetwork] Opportunity: Program Manager - Shared Research
 Facilities
Message-ID: <DM6PR03MB3449448AF067D842279B8DD5F8B29@DM6PR03MB3449.namprd03.prod.outlook.com>

Sharing a new opportunity at the University of Louisville, FYI:

Program Manager - Shared Research Facilities
https://www.higheredjobs.com/search/details.cfm?JobCode=178262057

Position Description:
The Program Manager will work closely with the Director of Shared Research Facilities to build, operate, and improve the university's coordinated support infrastructure for core (or shared) research facilities. This administrative infrastructure is an integral component of UofL's core facilities strategy and commitment to enhance the university's strategic focus on more effectively coordinating and managing its core facilities. The Program Manager will provide critical administrative support for core facilities across the university, including conducting analyses of core facility financial and operational data, supporting the university's core facility management software solution, providing business administration assistance to core facilities, and carrying out related activities.

Minimum Requirements:
Master's degree in a related field and five years of related experience. Additional experience may be used on a one-to-one basis to offset the educational requirements.

Preferred Qualifications:

  *   Program or project management experience
  *   Advanced Microsoft Excel skills with the ability to manipulate, analyze, interpret, and present data
  *   Experience with research universities or other research organizations
  *   Experience with research administration and core research facilities
  *   Experience with federal cost principles and regulations relevant to core facilities
  *   Competency in budget development and financial analysis
  *   Knowledge of cost accounting
  *   Experience with core facility management software solutions
  *   Experience with Microsoft Power BI or other business intelligence and data visualization software systems

Essential Duties and Responsibilities:

  *   Data Analysis - Conduct financial, operational, and other core facility data analyses, projections, and forecasts. Prepare reports for core directors, research leadership, and other stakeholders.
  *   Software Support - Serve as the lead for implementation and support of the university's core facility management software solution. Become a subject matter expert in the software, and support core personnel, researchers, and administrators in their use of the software. Collaborate with university offices on software implementation. Interface with the software vendor.
  *   Business Assistance - Assist core facilities with understanding costs, determining rates, adhering to compliance requirements, and managing revenues and expenditures. Develop expertise with federal cost principles and regulations relevant to cores. Develop and deliver core facility business and other training. Assist with administering university SOPs/manuals/policies related to core facilities.
  *   Other Program Management - Perform other activities as directed, including managing core facility review/evaluation processes, helping prepare for and support meetings of core facility advisory/governance structures, coordinating events, drafting communications and marketing materials, and engaging with internal and external stakeholders.

This position offers an opportunity for a flexible work environment and remote and hybrid work applicants will be considered.

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From na2661 at columbia.edu  Fri Mar  3 11:19:38 2023
From: na2661 at columbia.edu (Nava Ariel-Sternberg)
Date: Fri, 3 Mar 2023 11:19:38 -0500
Subject: [labnetwork] Mask plate vendors?
Message-ID: <005b01d94deb$f404aa20$dc0dfe60$@columbia.edu>

Happy Friday everyone!

Our litho mask plates' order from Tellic is seriously delayed and we are
running low on masks. 

We are searching for alternative vendors, any recommendations would be
greatly appreciated. 

Thanks,

Nava

 

Dr. Nava Ariel-Sternberg

Senior Director of CNI Labs

Columbia University

CEPSR/MC 8903 

530 west 120th st. NY

NY 10027

Office: 212-8549927

Cell: 201-5627600

 

 

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From price.798 at osu.edu  Fri Mar  3 12:17:08 2023
From: price.798 at osu.edu (Price, Aimee)
Date: Fri, 3 Mar 2023 17:17:08 +0000
Subject: [labnetwork] Mask plate vendors?
In-Reply-To: <005b01d94deb$f404aa20$dc0dfe60$@columbia.edu>
References: <005b01d94deb$f404aa20$dc0dfe60$@columbia.edu>
Message-ID: <CH0PR01MB7139A58AE9AE3B0DADBAA390BCB39@CH0PR01MB7139.prod.exchangelabs.com>

Hi Nava,
When we used to fab our own masks I purchased directly from Hoya.  Information Technology - HOYA Corporation<https://www.hoya.com/en/business/informationtechnology/>  I?m not sure if he is still there but Mark Jee was terrific to work with, JEE Mark mark.jee at hoya.com<mailto:mark.jee at hoya.com>.

I have a stock of EBL resist coated 4? and 5? mask blanks that are just sitting on the shelf. The 5? blanks are quartz with Cr and the AR coating, plus ZEP EBL resist.  We have successfully removed the resist and re-coated for MLA 150 exposure.  The 4? are similar but the resist is the old EBR9.  I?m not sure we have experience re-using these, but we do have them on hand.  If you are stuck and either of these sizes are useful to you, contact me directly.  We?d be happy to work something out.

Best,
Aimee

From: labnetwork <labnetwork-bounces at mtl.mit.edu> On Behalf Of Nava Ariel-Sternberg
Sent: Friday, March 3, 2023 11:20 AM
To: 'Fab Network' <labnetwork at mtl.mit.edu>
Subject: [labnetwork] Mask plate vendors?

Happy Friday everyone! Our litho mask plates? order from Tellic is seriously delayed and we are running low on masks. We are searching for alternative vendors, any recommendations would be greatly appreciated. Thanks,Nava Dr. Nava Ariel-SternbergSenior

Happy Friday everyone!
Our litho mask plates? order from Tellic is seriously delayed and we are running low on masks.
We are searching for alternative vendors, any recommendations would be greatly appreciated.
Thanks,
Nava

Dr. Nava Ariel-Sternberg
Senior Director of CNI Labs
Columbia University
CEPSR/MC 8903
530 west 120th st. NY
NY 10027
Office: 212-8549927
Cell: 201-5627600


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From grallion at ncsu.edu  Fri Mar  3 12:29:21 2023
From: grallion at ncsu.edu (Greg Allion)
Date: Fri, 3 Mar 2023 12:29:21 -0500
Subject: [labnetwork] Mask plate vendors?
In-Reply-To: <005b01d94deb$f404aa20$dc0dfe60$@columbia.edu>
References: <005b01d94deb$f404aa20$dc0dfe60$@columbia.edu>
Message-ID: <CAAFf2sBNcRiA-5LVun=R8semyvniVrfpSmrDzC1_F1PORME7cg@mail.gmail.com>

Hi Nava,
Try Nanofilm.
https://www.nanofilm.com/
Our blanks have rarely taken longer than a week to receive.
Best,
Greg

On Fri, Mar 3, 2023 at 11:50?AM Nava Ariel-Sternberg <na2661 at columbia.edu>
wrote:

> Happy Friday everyone!
>
> Our litho mask plates? order from Tellic is seriously delayed and we are
> running low on masks.
>
> We are searching for alternative vendors, any recommendations would be
> greatly appreciated.
>
> Thanks,
>
> Nava
>
>
>
> Dr. Nava Ariel-Sternberg
>
> Senior Director of CNI Labs
>
> Columbia University
>
> CEPSR/MC 8903
>
> 530 west 120th st. NY
>
> NY 10027
>
> Office: 212-8549927
>
> Cell: 201-5627600
>
>
>
>
> _______________________________________________
> labnetwork mailing list
> labnetwork at mtl.mit.edu
> https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork
>


-- 
Greg Allion
NC State University Nanofabrication Facility (NNF)
Process Integration Engineering Manager

Monteith Research Center
2410 Campus Shore Drive rm.243E
Raleigh, NC 27606
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From jim at photomaskportal.com  Fri Mar  3 13:05:46 2023
From: jim at photomaskportal.com (Jim Carroll)
Date: Fri, 3 Mar 2023 12:05:46 -0600
Subject: [labnetwork] Mask plate vendors?
In-Reply-To: <005b01d94deb$f404aa20$dc0dfe60$@columbia.edu>
References: <005b01d94deb$f404aa20$dc0dfe60$@columbia.edu>
Message-ID: <CACVEG9hyvqnJ+vHYD5oj3YnNjBopDQ7gDX6y9GmYL_XScDivRw@mail.gmail.com>

Hi Nava,

For mask blanks, you can contact NanoFilm.  They are also in the LA area.

https://www.nanofilm.com/

If you get in a real bind, let me know.

Thanks,
Jim Carroll
*PhotomaskPORTAL*
*We help you make masks*
(415) 448-6275

   -
   <http://www.photomaskportal.com>



On Fri, Mar 3, 2023 at 10:49?AM Nava Ariel-Sternberg <na2661 at columbia.edu>
wrote:

> Happy Friday everyone!
>
> Our litho mask plates? order from Tellic is seriously delayed and we are
> running low on masks.
>
> We are searching for alternative vendors, any recommendations would be
> greatly appreciated.
>
> Thanks,
>
> Nava
>
>
>
> Dr. Nava Ariel-Sternberg
>
> Senior Director of CNI Labs
>
> Columbia University
>
> CEPSR/MC 8903
>
> 530 west 120th st. NY
>
> NY 10027
>
> Office: 212-8549927
>
> Cell: 201-5627600
>
>
>
>
> _______________________________________________
> labnetwork mailing list
> labnetwork at mtl.mit.edu
> https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork
>
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From mhofheins at unm.edu  Fri Mar  3 13:29:15 2023
From: mhofheins at unm.edu (Mark Hofheins)
Date: Fri, 3 Mar 2023 18:29:15 +0000
Subject: [labnetwork] ME601  Veeco ION Mill
Message-ID: <BY5PR07MB7029BEB4FDAC7511356727B4A3B39@BY5PR07MB7029.namprd07.prod.outlook.com>

Hello All,
We have a Veeco ME601 ION Mill we are reserrecting and have parts of a manual for a ME1001.
Does anyone have a ME601 manual we could get a copy of or purchase?

Best regards,

Mark Hofheins

mhofheins at unm.edu<mailto:mhofheins at unm.edu>

Cell  505-259-9278

Office 505-272-7506



Micro Electronics Technician

Manufacturing Engineering/

School of Engineering

University of New Mexico MTTC

800 Bradbury S.E.  Suit 169

Albuquerque, New Mexico

87106-4346

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From Justin_Moreau at uml.edu  Fri Mar  3 15:50:37 2023
From: Justin_Moreau at uml.edu (Moreau, Justin)
Date: Fri, 3 Mar 2023 20:50:37 +0000
Subject: [labnetwork] Mask plate vendors?
In-Reply-To: <005b01d94deb$f404aa20$dc0dfe60$@columbia.edu>
References: <005b01d94deb$f404aa20$dc0dfe60$@columbia.edu>
Message-ID: <DM4PR02MB8910BE3907AE97118A6882EB95B39@DM4PR02MB8910.namprd02.prod.outlook.com>

Hi Nava

We use Nanofilm
2641 Townsgate #100
Westlake Village, CA 91361
www.nanofilm.com<http://www.nanofilm.com>

Last order took 2 weeks to receive.





<https://www.linkedin.com/company/umass-lowell-core-research-facilities/>[University of Massachusetts Lowell]
Justin Moreau
Sr. Lab Manager, Nanofabrication Core
CORE RESEARCH FACILITIES
ETIC
E: Justin_Moreau at uml.edu<mailto:Justin_Moreau at uml.edu>
T: 978-934-3615   M: 978-337-8148

[cid:image002.jpg at 01D94DE7.9549DBD0]<https://www.linkedin.com/company/umass-lowell-core-research-facilities/>

From: labnetwork <labnetwork-bounces at mtl.mit.edu> On Behalf Of Nava Ariel-Sternberg
Sent: Friday, March 3, 2023 11:20 AM
To: 'Fab Network' <labnetwork at mtl.mit.edu>
Subject: [labnetwork] Mask plate vendors?

CAUTION: This email was sent from outside the UMass Lowell network.

Happy Friday everyone!
Our litho mask plates' order from Tellic is seriously delayed and we are running low on masks.
We are searching for alternative vendors, any recommendations would be greatly appreciated.
Thanks,
Nava

Dr. Nava Ariel-Sternberg
Senior Director of CNI Labs
Columbia University
CEPSR/MC 8903
530 west 120th st. NY
NY 10027
Office: 212-8549927
Cell: 201-5627600


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From na2661 at columbia.edu  Mon Mar  6 08:07:51 2023
From: na2661 at columbia.edu (Nava Ariel-Sternberg)
Date: Mon, 6 Mar 2023 08:07:51 -0500
Subject: [labnetwork] Mask plate vendors?
In-Reply-To: <CACVEG9hyvqnJ+vHYD5oj3YnNjBopDQ7gDX6y9GmYL_XScDivRw@mail.gmail.com>
References: <005b01d94deb$f404aa20$dc0dfe60$@columbia.edu>
 <CACVEG9hyvqnJ+vHYD5oj3YnNjBopDQ7gDX6y9GmYL_XScDivRw@mail.gmail.com>
Message-ID: <015501d9502c$a88ff4d0$f9afde70$@columbia.edu>

Thanks Jim and everyone else who answered me, including via direct message. 

We placed an order with Nanofilm and the mask plates are expected today. 

Have a great week,

Nava

 

 

Dr. Nava Ariel-Sternberg

Senior Director of CNI Labs

Columbia University

CEPSR/MC 8903 

530 west 120th st. NY

NY 10027

Office: 212-8549927

Cell: 201-5627600

 

 

From: Jim Carroll <jim at photomaskportal.com> 
Sent: Friday, March 3, 2023 1:06 PM
To: Nava Ariel-Sternberg <na2661 at columbia.edu>
Cc: Fab Network <labnetwork at mtl.mit.edu>
Subject: Re: [labnetwork] Mask plate vendors?

 

Hi Nava,

 

For mask blanks, you can contact NanoFilm.  They are also in the LA area.

 

https://www.nanofilm.com/

 

If you get in a real bind, let me know.

 

Thanks,

Jim Carroll
PhotomaskPORTAL

We help you make masks
(415) 448-6275

*          <http://www.photomaskportal.com> 


 

 

On Fri, Mar 3, 2023 at 10:49?AM Nava Ariel-Sternberg <na2661 at columbia.edu <mailto:na2661 at columbia.edu> > wrote:

Happy Friday everyone!

Our litho mask plates? order from Tellic is seriously delayed and we are running low on masks. 

We are searching for alternative vendors, any recommendations would be greatly appreciated. 

Thanks,

Nava

 

Dr. Nava Ariel-Sternberg

Senior Director of CNI Labs

Columbia University

CEPSR/MC 8903 

530 west 120th st. NY

NY 10027

Office: 212-8549927

Cell: 201-5627600

 

 

_______________________________________________
labnetwork mailing list
labnetwork at mtl.mit.edu <mailto:labnetwork at mtl.mit.edu> 
https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork

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From dilan.ratnayake at louisville.edu  Mon Mar  6 14:44:00 2023
From: dilan.ratnayake at louisville.edu (Ratnayake, Dilan)
Date: Mon, 6 Mar 2023 19:44:00 +0000
Subject: [labnetwork] Plasma-Therm Technical Workshop at University of
 Louisville
Message-ID: <BN9PR03MB618711D839019960C2E3367488B69@BN9PR03MB6187.namprd03.prod.outlook.com>

Dear Colleagues,

NSF NNCI KY Multiscale and the Plasma-Therm are presenting a technical workshop in Louisville, KY on Tuesday, April 11th for Fundamentals of Plasma Processing (Etching and Deposition). The workshop will be held in room 139 of the Shumaker Research Building on the Belknap campus. Please see the attached flyer for more information.
Registration for the workshop is free, and breakfast and lunch will be provided. I kindly request that you share this information with your research community and encourage them to register as soon as possible if they are interested. (Registration is limited to 60 participants)

You can find the registration link here: http://www.kymultiscale.net/workshop-registration

Thank you for your time and consideration.


Dr. Dilan Ratnayake

KY Multiscale

http://www.kymultiscale.net<http://www.kymultiscale.net/>

[cid:86238d70-b918-4c80-a958-0de1024bd7d8]

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From aamer.mahmood at mail.wvu.edu  Mon Mar  6 15:51:21 2023
From: aamer.mahmood at mail.wvu.edu (Aamer Mahmood)
Date: Mon, 6 Mar 2023 20:51:21 +0000
Subject: [labnetwork] Open position for Manager of the WVU Microfabrication
 Facilities
Message-ID: <BYAPR03MB36406C0288CF2BE82A59FE32CAB69@BYAPR03MB3640.namprd03.prod.outlook.com>

Dear colleagues,
Please help spread the word to fill the position for a Manager of the WVU cleanrooms in Morgantown, WV. Details can be found at

https://wvu.taleo.net/careersection/wvu_research/jobdetail.ftl?job=21506&tz=GMT-05%3A00&tzname=America%2FNew_York

Interested candidates can reach out to me directly for further information.
Thanks,

--
Aamer Mahmood
Director
Shared Research Facilities
West Virginia University
Morgantown, WV

(304) 293 9418 (work)
https://sharedresearchfacilities.wvu.edu/

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From s.siontas at lelantostech.com  Tue Mar  7 12:25:23 2023
From: s.siontas at lelantostech.com (Stylianos Siontas)
Date: Tue, 7 Mar 2023 12:25:23 -0500
Subject: [labnetwork] Columbia University Startup seeking to hire Engineer
Message-ID: <CAPcjk-wSsvp980-2p34McrNi_CjuURMDM8HBd3x8FZi0QvU4BA@mail.gmail.com>

Dear all,

''Lelantos is a startup developing novel gas sensors targeted to IoT
applications in environmental and air quality monitoring, threat detection
and medical diagnostics markets. We are seeking to hire a Senior Product
Engineer to join our fast growing team in New York City.''

Please see attached job description and feel free to share with fitting
candidates.
-- 

Stylianos Siontas | PhD

Co-founder & CEO | Lelantos

s.siontas at lelantostech.com

www.lelantostech.com
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From meredith.metzler at nist.gov  Tue Mar  7 15:15:10 2023
From: meredith.metzler at nist.gov (Metzler, Meredith G. (Fed))
Date: Tue, 7 Mar 2023 20:15:10 +0000
Subject: [labnetwork] Cryo-piping contractors for LN2 piping sought
In-Reply-To: <CANxZiKo0-R4kNsn2wh+q+NCTQ9XsVyweoZzeV7PMz0=zXKKYtA@mail.gmail.com>
References: <DM6PR11MB316257914858687CD6BC5570D7AC9@DM6PR11MB3162.namprd11.prod.outlook.com>
 <AC.4F.08004.C66BEF36@smtp02.aqua.bos.sync.lan>
 <CANxZiKo0-R4kNsn2wh+q+NCTQ9XsVyweoZzeV7PMz0=zXKKYtA@mail.gmail.com>
Message-ID: <DM6PR09MB5238EA02054BE2073DD415B0F7B79@DM6PR09MB5238.namprd09.prod.outlook.com>

Hi Everyone,

Thank you all for the helpful responses.

Regards,

Meredith Metzler
National Institute of Standards and Technology, Physical Measurement Laboratory
Process Engineer ? Center for Nanoscale Science and Technology Facility, NanoFab
100 Bureau Drive, Mail Stop 6201, Building 216
Gaithersburg, MD 20899
301-975-8187
meredith.metzler at nist.gov<mailto:meredith.metzler at nist.gov>
https://www.nist.gov/cnst


From: Timothy Fuller <tafuller at eng.ucsd.edu>
Sent: Wednesday, March 1, 2023 11:44 AM
To: johnboyle <johnboyle at fast.net>
Cc: Collins, Deon <deonc69 at illinois.edu>; Metzler, Meredith G. (Fed) <meredith.metzler at nist.gov>; labnetwork at mtl.mit.edu
Subject: Re: [labnetwork] Cryo-piping contractors for LN2 piping sought

When I worked at HRL our original installation had KF 25 Buna-N o-rings for the vacuum jacket.  After replacing them with Viton o-rings, the vacuum jacket was leak tight.

On Wed, Mar 1, 2023 at 4:45?AM johnboyle <johnboyle at fast.net<mailto:johnboyle at fast.net>> wrote:
Check Acme Cryogenics, Allentown, PA. They make VIP, phase separators, do installation and repairs. Ask for Field Services

John Boyle



Sent from my Verizon, Samsung Galaxy smartphone


-------- Original message --------
From: "Collins, Deon" <deonc69 at illinois.edu<mailto:deonc69 at illinois.edu>>
Date: 2/28/23 7:46 PM (GMT-05:00)
To: "Metzler, Meredith G. (Fed)" <meredith.metzler at nist.gov<mailto:meredith.metzler at nist.gov>>, labnetwork at mtl.mit.edu<mailto:labnetwork at mtl.mit.edu>
Subject: Re: [labnetwork] Cryo-piping contractors for LN2 piping sought

Your vacuum jacket has failed. We are going through the same situation with our static LN2 delivery lines.

Is your phase separator a Static or Dynamic system?

From: labnetwork <labnetwork-bounces at mtl.mit.edu<mailto:labnetwork-bounces at mtl.mit.edu>> On Behalf Of Metzler, Meredith G. (Fed)
Sent: Tuesday, February 28, 2023 2:08 PM
To: labnetwork at mtl.mit.edu<mailto:labnetwork at mtl.mit.edu>
Subject: [labnetwork] Cryo-piping contractors for LN2 piping sought

We are hoping the community can assist us in identifying a vendor who can inspect an existing LN2 delivery piping system in the cleanroom for our cryo-etch tools. We've recently started experiencing issues with a phase separator that keeps building up a large block of ice on the outside of it.

We have a 5 Gallon phase separator made by Chart Inc. with one outlet. It feeds liquid nitrogen to several tools in the etch bay of the cleanroom. The LN2 system is house regulated to 40 PSI at the inlet. The unit separates the gaseous N2 from the liquid. The liquid is stored in the 5 gallon volume surrounded by a vacuum jacket to prevent icing. The final LN2 inlet connection to the phase separator, the exhaust connection, and the over pressure relief connection seem to be the biggest points of failure. At these three points we have cold air and moisture condensation that forms an ice ball.

Although, we have made many at wrapping and insulating these connection points, we cannot quite get the coverage to eliminate this ice ball.

Does the community have any preferred cryo-piping contractors they can recommend to assist with solving this issue and any of our future cryo-piping needs?

Thanks!

Meredith Metzler
National Institute of Standards and Technology, Physical Measurement Laboratory
Process Engineer ? Center for Nanoscale Science and Technology Facility, NanoFab
100 Bureau Drive, Mail Stop 6201, Building 216
Gaithersburg, MD 20899
301-975-8187
meredith.metzler at nist.gov<mailto:meredith.metzler at nist.gov>
https://www.nist.gov/cnst<https://gcc02.safelinks.protection.outlook.com/?url=https%3A%2F%2Furldefense.com%2Fv3%2F__https%3A%2Fwww.nist.gov%2Fcnst__%3B!!DZ3fjg!-6Lfwk5cCgFK0WcjbkRqEZm2A8T7loqa2OV_9x-WW72ajmC1A4euSzW2VyRMpj0J8yR1_DdWvG0axt3nRQj-R1EmQJ2lypVZ%24&data=05%7C01%7Cmeredith.metzler%40nist.gov%7Cf95391a790e34259dfc408db1a74248c%7C2ab5d82fd8fa4797a93e054655c61dec%7C1%7C0%7C638132858369919538%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=FpntaUfl0pARpQK82TN%2F36q6F7PRiT635RFPG5rlBxM%3D&reserved=0>

_______________________________________________
labnetwork mailing list
labnetwork at mtl.mit.edu<mailto:labnetwork at mtl.mit.edu>
https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork<https://gcc02.safelinks.protection.outlook.com/?url=https%3A%2F%2Fmtl.mit.edu%2Fmailman%2Flistinfo.cgi%2Flabnetwork&data=05%7C01%7Cmeredith.metzler%40nist.gov%7Cf95391a790e34259dfc408db1a74248c%7C2ab5d82fd8fa4797a93e054655c61dec%7C1%7C0%7C638132858369919538%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=jY7yi1EGrLw%2FLeum9rmIqWagunkIebrtrNsdJIaxNB0%3D&reserved=0>
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From sbjones at uw.edu  Wed Mar  8 12:20:19 2023
From: sbjones at uw.edu (Sarice Jones)
Date: Wed, 8 Mar 2023 09:20:19 -0800
Subject: [labnetwork] Strasbaugh 7AA Grinder failure advice
Message-ID: <CAP9r4frGYSkp9nVnLdrJ7i5GS4-5koe1aoPsNnRX9wCexZWuaw@mail.gmail.com>

Dear Lab Network, particularly members who've had to coax 80s tools back to
life,

At the University of Washington's WNF, we have a Strasbaugh 7AA grinder via
Axus that is failing. The wafer thickness measurement, which gates
initializing and processing, has been corrupted (we believe somewhere in
the G&L board cage, the signal is accurate up to there) and the tool can't
proceed.

Specifics on the behavior we're seeing:
- 0 measurement brings back 6560 microns
- thickness measurements are nonlinearly subtracted rather than added to
this: e.g. expected measurement of 600 brings back 5460
- bottoms out at about 2640

Getting replacement boards is going slowly and we're interested in a
workaround that's preferably a step above manual mode. Is anyone familiar
with the Strasbaugh 7AA or similar tools who has advice? Some of our ideas
include:
- Reset EPROM board/chips
- Force the tool to accept an initialization sequence (wafer thickness can
be backfilled as long as the initialization is accepted)
- Get into the ladder logic of the tool

Any advice or experience is much appreciated. Regards,

Sarice
-- 


Sarice B. Jones

Facilities Engineer, Washington Nanofabrication Facility (WNF)

University of Washington, Fluke Hall 115

(206) 685-7757
sbjones at uw.edu
http://www.wnf.washington.edu/
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From lopezg at seas.upenn.edu  Thu Mar  9 08:31:52 2023
From: lopezg at seas.upenn.edu (Gerald Lopez)
Date: Thu, 9 Mar 2023 08:31:52 -0500
Subject: [labnetwork] JOB OPPORTUNITY: Electron Microscopy Trainer and
 Support Specialist at UPenn Singh Center
Message-ID: <CAERBAG-RbXxKSe3eysxd36zNDTEpEa0ZuQDscrcoU6bQX5OWmg@mail.gmail.com>

Dear Colleagues:

We've created a new position
<https://wd1.myworkdaysite.com/en-US/recruiting/upenn/careers-at-penn/details/Electron-Microscopy-Trainer-and-Support-Specialist---Nanoscale-Characterization-Facility---Penn-Engineering_JR00068909?q=Singh%20Center>
to assist with our electron microscopy training and support at the Singh
Center for Nanotechnology <http://nano.upenn.edu/> Nanoscale
Characterization Facility. If you are interested in working at a
state-of-the-art facility, you can apply
<https://wd1.myworkdaysite.com/en-US/recruiting/upenn/careers-at-penn/details/Electron-Microscopy-Trainer-and-Support-Specialist---Nanoscale-Characterization-Facility---Penn-Engineering_JR00068909?q=Singh%20Center>
using the link below.

We're hiring: *Electron Microscopy Trainer and Support Specialist* -
Nanoscale Characterization Facility at the *University of Pennsylvania*
Singh Center for Nanotechnology
https://wd1.myworkdaysite.com/en-US/recruiting/upenn/careers-at-penn/details/Electron-Microscopy-Trainer-and-Support-Specialist---Nanoscale-Characterization-Facility---Penn-Engineering_JR00068909?q=Singh%20Center

Sincerely,
Gerald

Gerald G. Lopez, Ph.D. (he/him/his)

Director of Operations and Business Development & Center Associate Director

University of Pennsylvania | Singh Center for Nanotechnology

NNCI Mid-Atlantic Nanotechnology Hub (MANTH) ? nnci.net

3205 Walnut Street, Philadelphia, PA 19104 USA Deliveries: 3231 Walnut
Street, LRSM Building, Philadelphia, PA 19104

nano.upenn.edu ? lopezg at seas.upenn.edu ? +1-215-573-4041 ?
linkedin.com/in/geraldglopez/
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From zlewicka at princeton.edu  Fri Mar 10 11:39:09 2023
From: zlewicka at princeton.edu (Zuzanna A. Lewicka)
Date: Fri, 10 Mar 2023 16:39:09 +0000
Subject: [labnetwork] Technical Leadership Opportunity: The Director of the
 Micro/Nanofabrication Center (MNFC) at Princeton Materials Institute
Message-ID: <DM6PR04MB6363E6E807CCE8E71CE84AD1D2BA9@DM6PR04MB6363.namprd04.prod.outlook.com>

Sharing a new opportunity at Princeton University.  Please check out the job posing and distribute within your networks:
https://puwebp.princeton.edu/AcadHire/apply/application.xhtml?listingId=29441

More information on PMI can be found at materials.princeton.edu

Best regards,
Zuzanna Lewicka
--------------------------------

Micro/Nanofabrication Center (MNFC)
Princeton University
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From lopezg at seas.upenn.edu  Tue Mar 14 17:42:40 2023
From: lopezg at seas.upenn.edu (Gerald Lopez)
Date: Tue, 14 Mar 2023 17:42:40 -0400
Subject: [labnetwork] Seeking Opinions on Lab Management Software
Message-ID: <CAERBAG-YEN7GmWMWGimJRRBEyyFegZz8=GggboYnvORFYhHEsg@mail.gmail.com>

Dear Colleagues:

Would anyone on our network with experience working with both
Stratocore's lab management software (Home - Stratocore
<https://www.stratocore.com/>) and NEMO be willing to share their thoughts
on these systems? If you work with Stratocore, can you kindly share its
pros and cons? What were your reasons if you moved from NEMO to Stratocore
or vice versa?

Best,
Gerald

Gerald G. Lopez, Ph.D. (he/him/his)

Director of Operations and Business Development & Center Associate Director

University of Pennsylvania | Singh Center for Nanotechnology

NNCI Mid-Atlantic Nanotechnology Hub (MANTH) ? nnci.net

3205 Walnut Street, Philadelphia, PA 19104 USA Deliveries: 3231 Walnut
Street, LRSM Building, Philadelphia, PA 19104

nano.upenn.edu ? lopezg at seas.upenn.edu ? +1-215-573-4041 ?
linkedin.com/in/geraldglopez/
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From philippe.fluckiger at epfl.ch  Wed Mar 15 06:18:46 2023
From: philippe.fluckiger at epfl.ch (=?utf-8?B?RmzDvGNraWdlciBQaGlsaXBwZQ==?=)
Date: Wed, 15 Mar 2023 10:18:46 +0000
Subject: [labnetwork] Seeking Opinions on Lab Management Software
In-Reply-To: <CAERBAG-YEN7GmWMWGimJRRBEyyFegZz8=GggboYnvORFYhHEsg@mail.gmail.com>
References: <CAERBAG-YEN7GmWMWGimJRRBEyyFegZz8=GggboYnvORFYhHEsg@mail.gmail.com>
Message-ID: <af8162d1fcb54e3d890d885c920b2322@epfl.ch>

Hello Gerald, Dear Folks and Friends,

I hope you are all doing well.

In the following months, we are going to evaluate how STRATOCORE can be adapted to the specific needs of our state-of-the art platform.

Access control (physical interlock on every tool), conditional reservations depending of the targets installed on sputters/evaporators will be the key points to address.

We will see how STRATOCORE is willing to be responsive and motivated to proceed to our demands, and what add-ons might be made by EPFL.

Currently we are still running our homemade 20+ years old permanently upgraded software but we are reaching the limits of it.

The reason we will investigate STRATOCORE is that it is already implemented in Life Science at EPFL.

This is definitely a hot topic !

Regards,
Philippe

Dr Philippe Fl?ckiger
Director of Operations
http://cmi.epfl.ch/
Phone +41 21 693 6695

From: labnetwork <labnetwork-bounces at mtl.mit.edu> On Behalf Of Gerald Lopez
Sent: mardi, 14 mars 2023 22:43
To: labnetwork at mtl.mit.edu
Subject: [labnetwork] Seeking Opinions on Lab Management Software

Dear Colleagues:

Would anyone on our network with experience working with both Stratocore's lab management software (Home - Stratocore<https://www.stratocore.com/>) and NEMO be willing to share their thoughts on these systems? If you work with Stratocore, can you kindly share its pros and cons? What were your reasons if you moved from NEMO to Stratocore or vice versa?

Best,
Gerald


[https://lh5.googleusercontent.com/NUqjkaspQaBTb7N06qB3MRywBg5w4pDGo_OuUGZrMj3ewACFau26SJnRwTvMgc-YDXpSM3-qTmY_iqr-ttCJgr1M-OKuod2NDI9FwckJCRLEPfwAmDaX6bsMpi0ihlYL0fZqTvJc]


Gerald G. Lopez, Ph.D. (he/him/his)

Director of Operations and Business Development & Center Associate Director

University of Pennsylvania | Singh Center for Nanotechnology

NNCI Mid-Atlantic Nanotechnology Hub (MANTH) ? nnci.net<http://nnci.net/>

3205 Walnut Street, Philadelphia, PA 19104 USA Deliveries: 3231 Walnut Street, LRSM Building, Philadelphia, PA 19104

nano.upenn.edu<http://nano.upenn.edu/> ? lopezg at seas.upenn.edu<mailto:lopezg at seas.upenn.edu> ? +1-215-573-4041 ? linkedin.com/in/geraldglopez/<http://linkedin.com/in/geraldglopez/>


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From lopezg at seas.upenn.edu  Wed Mar 15 14:37:33 2023
From: lopezg at seas.upenn.edu (Gerald Lopez)
Date: Wed, 15 Mar 2023 14:37:33 -0400
Subject: [labnetwork] Seeking Opinions on Lab Management Software
In-Reply-To: <af8162d1fcb54e3d890d885c920b2322@epfl.ch>
References: <CAERBAG-YEN7GmWMWGimJRRBEyyFegZz8=GggboYnvORFYhHEsg@mail.gmail.com>
 <af8162d1fcb54e3d890d885c920b2322@epfl.ch>
Message-ID: <CAERBAG-+Mvoo-PZ_jrqfz6NfkR688tTL10-DYVPSonTE1DkgLQ@mail.gmail.com>

Philippe and Colleagues,

Thanks for the feedback. We are reviewing Stratocore at the moment as part
of a last minute due diligence.

In our brief assessment, it seems that Stratocore was designed particularly
for microscopy cores for *tool access control*, and while there is some
operational overlap with running a cleanroom, absent is *area access
control* as we charge and track access to parts of our cleanroom, which
NEMO does well. A few of us have found that reserving tools is a bit clunky
using the Stratocore calendar interface. NEMO's calendar is a bit more
intuitive and has the ability to provide a cleaner view of one's schedule.
This is especially important when running a multi-tool process, and you
want to plan your day accordingly with *fewer clicks*.

Looking at three specific categories of Annual Cost of Ownership,
Flexibility, and Feature Richness:

   1. *Annual Cost of Ownership*: Stratocore is significantly more
   expensive than NEMO. NEMO can be installed without vendor lock-in (no
   service agreement). And for about the same price year-to-year, we could
   push Atlantis to develop more into NEMO on our behalf for
   our specific processes and impact a larger community.
   2. *Flexibility*:  Stratocore is closed source and feature
   implementation is dependent on the development team's decision.  NEMO is
   community driven; anyone can contribute and their source code can be
   modified. For those not familiar, NEMO is extendable by way of plug-ins or
   you can completely branch out like our PennState colleagues.
   3. *Feature Richness*: While initially there are many well-thought out
   features in Statocore when it comes to billing, tool training requests,
   etc., the community contribution aspect of NEMO could easily outpace these
   over time.

Cost aside, I believe flexibility wins especially when there is community
involvement (similar to my days with GenISys and the ecosystem they created
with its customer base and user meetings). I am looking for a positive
difference of opinion if there are any. So far, I have heard none from our
network here but am open to them and a deeper discussion on our process
so far.

I agree with Philippe that this is a very hot topic for sure.

Best,
Gerald

Gerald G. Lopez, Ph.D. (he/him/his)

Director of Operations and Business Development & Center Associate Director

University of Pennsylvania | Singh Center for Nanotechnology

NNCI Mid-Atlantic Nanotechnology Hub (MANTH) ? nnci.net

3205 Walnut Street, Philadelphia, PA 19104 USA Deliveries: 3231 Walnut
Street, LRSM Building, Philadelphia, PA 19104

nano.upenn.edu ? lopezg at seas.upenn.edu ? +1-215-573-4041 ?
linkedin.com/in/geraldglopez/


On Wed, Mar 15, 2023 at 6:18?AM Fl?ckiger Philippe <
philippe.fluckiger at epfl.ch> wrote:

> Hello Gerald, Dear Folks and Friends,
>
>
>
> I hope you are all doing well.
>
>
>
> In the following months, we are going to evaluate how STRATOCORE can be
> adapted to the specific needs of our state-of-the art platform.
>
>
>
> Access control (physical interlock on every tool), conditional
> reservations depending of the targets installed on sputters/evaporators
> will be the key points to address.
>
>
>
> We will see how STRATOCORE is willing to be responsive and motivated to
> proceed to our demands, and what add-ons might be made by EPFL.
>
>
>
> Currently we are still running our homemade 20+ years old permanently
> upgraded software but we are reaching the limits of it.
>
>
>
> The reason we will investigate STRATOCORE is that it is already
> implemented in Life Science at EPFL.
>
>
>
> This is definitely a hot topic !
>
>
>
> Regards,
>
> Philippe
>
>
>
> *Dr Philippe Fl?ckiger*
>
> *Director of Operations*
>
> *http://cmi.epfl.ch/
> <https://urldefense.com/v3/__http://cmi.epfl.ch/__;!!IBzWLUs!XNt7jKZP_y-F055dlRPn4AEPFGQRT5T7HMCrEM3DLLO_gMCbSJPyAQRkeQ1JTvBMqYTWGQERJfgNOaS44Fxqg8jwU37J22mH$>*
>
> *Phone +41 21 693 6695*
>
>
>
> *From:* labnetwork <labnetwork-bounces at mtl.mit.edu> *On Behalf Of *Gerald
> Lopez
> *Sent:* mardi, 14 mars 2023 22:43
> *To:* labnetwork at mtl.mit.edu
> *Subject:* [labnetwork] Seeking Opinions on Lab Management Software
>
>
>
> Dear Colleagues:
>
>
>
> Would anyone on our network with experience working with both
> Stratocore's lab management software (Home - Stratocore
> <https://urldefense.com/v3/__https://www.stratocore.com/__;!!IBzWLUs!XNt7jKZP_y-F055dlRPn4AEPFGQRT5T7HMCrEM3DLLO_gMCbSJPyAQRkeQ1JTvBMqYTWGQERJfgNOaS44Fxqg8jwU17eSWid$>)
> and NEMO be willing to share their thoughts on these systems? If you work
> with Stratocore, can you kindly share its pros and cons? What were your
> reasons if you moved from NEMO to Stratocore or vice versa?
>
>
>
> Best,
>
> Gerald
>
>
>
> *Gerald G. Lopez, Ph.D. *(he/him/his)
>
> Director of Operations and Business Development & Center Associate Director
>
> University of Pennsylvania | Singh Center for Nanotechnology
>
> NNCI Mid-Atlantic Nanotechnology Hub (MANTH) ? nnci.net
> <https://urldefense.com/v3/__http://nnci.net/__;!!IBzWLUs!XNt7jKZP_y-F055dlRPn4AEPFGQRT5T7HMCrEM3DLLO_gMCbSJPyAQRkeQ1JTvBMqYTWGQERJfgNOaS44Fxqg8jwUzmJjuMu$>
>
> 3205 Walnut Street, Philadelphia, PA 19104 USA Deliveries: 3231 Walnut
> Street, LRSM Building, Philadelphia, PA 19104
>
> nano.upenn.edu ? lopezg at seas.upenn.edu ? +1-215-573-4041 ?
> linkedin.com/in/geraldglopez/
> <https://urldefense.com/v3/__http://linkedin.com/in/geraldglopez/__;!!IBzWLUs!XNt7jKZP_y-F055dlRPn4AEPFGQRT5T7HMCrEM3DLLO_gMCbSJPyAQRkeQ1JTvBMqYTWGQERJfgNOaS44Fxqg8jwUyMV3ZO8$>
>
>
>
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From robert.macdonald at ge.com  Mon Mar 20 10:52:03 2023
From: robert.macdonald at ge.com (Macdonald, Robert (GE Research, US))
Date: Mon, 20 Mar 2023 14:52:03 +0000
Subject: [labnetwork] ESI 5200 Laser maintenance company
Message-ID: <8525cb2c527f44278ca6f43e44cce710@ge.com>

Hi All,

We have an old, unsupported ESI 5200 Laser we use primarily for cutting large format plastic films.

We are looking for a field service engineer who still supports these tools.

If anyone has a line for such a service we would be most appreciative.

Thank you,

Robert MacDonald
MEMS Engineer
GE Research
1 Research Circle
Niskayuna, NY 12309
518 312-5646
Robert.macdonald at ge.com

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From julia.aebersold at louisville.edu  Mon Mar 20 18:26:17 2023
From: julia.aebersold at louisville.edu (Aebersold, Julia)
Date: Mon, 20 Mar 2023 22:26:17 +0000
Subject: [labnetwork] Habitual late payments from external clients
Message-ID: <DM5PR03MB30987B3B2F18AFA721871A2786809@DM5PR03MB3098.namprd03.prod.outlook.com>

Hello everyone.  We have a few external clients that are habitual late payers for their invoices.

How does your facility deal with these late payers?  I'm thinking of applying an interest payment after a certain time period similar to credit card companies, but I want to hear what others do to encourage clients to pay on time.

Cheers!

Julia Aebersold, Ph.D.
Manager, Micro/Nano Technology Center
University of Louisville
Shumaker Research Building, Room 233
2210 South Brook Street
Louisville, KY  40292
(502) 852-1572

http://louisville.edu/micronano/

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From lopezg at seas.upenn.edu  Tue Mar 21 08:14:11 2023
From: lopezg at seas.upenn.edu (Gerald Lopez)
Date: Tue, 21 Mar 2023 08:14:11 -0400
Subject: [labnetwork] Habitual late payments from external clients
In-Reply-To: <DM5PR03MB30987B3B2F18AFA721871A2786809@DM5PR03MB3098.namprd03.prod.outlook.com>
References: <DM5PR03MB30987B3B2F18AFA721871A2786809@DM5PR03MB3098.namprd03.prod.outlook.com>
Message-ID: <CAERBAG93xG4FawF_dFq+MFY3KxrkA=enY-0qzH1NLtvY0raSVQ@mail.gmail.com>

Hi Julia -

Great question. I assume this is for external corporate users? We had a
similar problem. Other than cutting off access, we put in preventative
measures. We have a prepayment program that the external users can use to
draw down their credit. This is similar to larger companies who authorize a
PO for a specific amount to not exceed their allocated budget for a project
as we invoice against it.

Best,
Gerald

Gerald G. Lopez, Ph.D. (he/him/his)

Director of Operations and Business Development & Center Associate Director

University of Pennsylvania | Singh Center for Nanotechnology

NNCI Mid-Atlantic Nanotechnology Hub (MANTH) ? nnci.net

3205 Walnut Street, Philadelphia, PA 19104 USA Deliveries: 3231 Walnut
Street, LRSM Building, Philadelphia, PA 19104

nano.upenn.edu ? lopezg at seas.upenn.edu ? +1-215-573-4041 ?
linkedin.com/in/geraldglopez/


On Tue, Mar 21, 2023 at 7:39?AM Aebersold, Julia <
julia.aebersold at louisville.edu> wrote:

> Hello everyone.  We have a few external clients that are habitual late
> payers for their invoices.
>
>
>
> How does your facility deal with these late payers?  I?m thinking of
> applying an interest payment after a certain time period similar to credit
> card companies, but I want to hear what others do to encourage clients to
> pay on time.
>
>
>
> Cheers!
>
>
>
> Julia Aebersold, Ph.D.
>
> Manager, Micro/Nano Technology Center
>
> University of Louisville
>
> Shumaker Research Building, Room 233
>
> 2210 South Brook Street
>
> Louisville, KY  40292
>
> (502) 852-1572
>
>
>
> http://louisville.edu/micronano/
> <https://urldefense.com/v3/__http://louisville.edu/micronano/__;!!IBzWLUs!XV3aHT9ZSCPBdc3Lpr73dGmgwWYNGgYxxB4fLuNFuTfFVFPnPTzigm363tLBkIJeIDKg8GaQ5DhhO4JqRsCqBc9CSg3y13DapTME$>
>
>
> _______________________________________________
> labnetwork mailing list
> labnetwork at mtl.mit.edu
>
> https://urldefense.com/v3/__https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork__;!!IBzWLUs!XV3aHT9ZSCPBdc3Lpr73dGmgwWYNGgYxxB4fLuNFuTfFVFPnPTzigm363tLBkIJeIDKg8GaQ5DhhO4JqRsCqBc9CSg3y1zKaVNAy$
>
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From na2661 at columbia.edu  Tue Mar 21 09:34:00 2023
From: na2661 at columbia.edu (Nava Ariel-Sternberg)
Date: Tue, 21 Mar 2023 09:34:00 -0400
Subject: [labnetwork] Habitual late payments from external clients
In-Reply-To: <DM5PR03MB30987B3B2F18AFA721871A2786809@DM5PR03MB3098.namprd03.prod.outlook.com>
References: <DM5PR03MB30987B3B2F18AFA721871A2786809@DM5PR03MB3098.namprd03.prod.outlook.com>
Message-ID: <00dc01d95bf9$cbe99ed0$63bcdc70$@columbia.edu>

Hi Julia, all, 

Do external users sign a legal agreement to use your facility? 

To use our facility, external users sign a legal agreement (we have a
template phrased by our OGC who also reviews any requested changes to the
template). Payment is part of the terms and conditions of using our
facilities.

We send invoices monthly and if users are late, after a few reminders and
warnings, they get blocked from using our facility and usually that helps to
get them to pay. 

In a couple of cases we had to involve the GC to send specific companies
letters. One of the companies paid most of the debt after receiving the
letter. The other one was too small and the dollar amount was too small to
chase but they are blocked in our system from using the labs, ever again. 

As for applying interest payment, not sure if the recharge center guidelines
allow that, but even if they do, I wouldn't want to go that route because of
the overhead of just managing this on your side. I don't know how your
billing system works but these are just my thoughts. 

-Nava

 

Dr. Nava Ariel-Sternberg

Senior Director of CNI Labs

Columbia University

CEPSR/MC 8903 

530 west 120th st. NY

NY 10027

Office: 212-8549927

Cell: 201-5627600

 

 

From: labnetwork <labnetwork-bounces at mtl.mit.edu> On Behalf Of Aebersold,
Julia
Sent: Monday, March 20, 2023 6:26 PM
To: 'labnetwork at mtl.mit.edu' <labnetwork at mtl.mit.edu>
Subject: [labnetwork] Habitual late payments from external clients

 

Hello everyone.  We have a few external clients that are habitual late
payers for their invoices.  

 

How does your facility deal with these late payers?  I'm thinking of
applying an interest payment after a certain time period similar to credit
card companies, but I want to hear what others do to encourage clients to
pay on time.

 

Cheers!

 

Julia Aebersold, Ph.D.

Manager, Micro/Nano Technology Center

University of Louisville

Shumaker Research Building, Room 233

2210 South Brook Street

Louisville, KY  40292

(502) 852-1572

 

 <http://louisville.edu/micronano/> http://louisville.edu/micronano/

 

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From codreanu at udel.edu  Tue Mar 21 16:24:50 2023
From: codreanu at udel.edu (Iulian Codreanu)
Date: Tue, 21 Mar 2023 16:24:50 -0400
Subject: [labnetwork] Habitual late payments from external clients
In-Reply-To: <DM5PR03MB30987B3B2F18AFA721871A2786809@DM5PR03MB3098.namprd03.prod.outlook.com>
References: <DM5PR03MB30987B3B2F18AFA721871A2786809@DM5PR03MB3098.namprd03.prod.outlook.com>
Message-ID: <ddfe5923-9dd0-cca1-189b-83f08aa40036@udel.edu>

Hi Julia,

Here at UD, our cashier's office sends out monthly invoices to external 
users on our behalf. The nice thing about it is that the cashier's 
office transfers money into our account based on the invoiced amounts.

We are of course responsible for contacting the customers who are late 
on their payments. We have not had to enlist the help of any collection 
agencies (the user agreement would come in handy) but I had to remind 
some folks that some of their invoices were "very past due", i.e. over 
120 days. So far we were able to have our invoices paid but it takes 
some effort from the person who does our billing and from me.

I do not know how well a suggestion to charge interest on late payments 
would be received by my finance folks when I am not allowed to pass on 
the credit card fees for those who use that payment method.

Cheers,

Iulian








iulian Codreanu, Ph.D.
Director, Nanofabrication Facility
University of Delaware
Harker ISE Lab, Room 163
221 Academy Street
Newark, DE 19716
302-831-2784
https://udnf.udel.edu

On 3/20/2023 6:26 PM, Aebersold, Julia wrote:
>
> Hello everyone.? We have a few external clients that are habitual late 
> payers for their invoices.
>
> How does your facility deal with these late payers?? I?m thinking of 
> applying an interest payment after a certain time period similar to 
> credit card companies, but I want to hear what others do to encourage 
> clients to pay on time.
>
> Cheers!
>
> Julia Aebersold, Ph.D.
>
> Manager, Micro/Nano Technology Center
>
> University of Louisville
>
> Shumaker Research Building, Room 233
>
> 2210 South Brook Street
>
> Louisville, KY 40292
>
> (502) 852-1572
>
> http://louisville.edu/micronano/ <http://louisville.edu/micronano/>
>
>
> _______________________________________________
> labnetwork mailing list
> labnetwork at mtl.mit.edu
> https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork
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From mmoneck at andrew.cmu.edu  Tue Mar 21 20:26:04 2023
From: mmoneck at andrew.cmu.edu (Matthew Moneck)
Date: Tue, 21 Mar 2023 20:26:04 -0400
Subject: [labnetwork] Habitual late payments from external clients
In-Reply-To: <DM5PR03MB30987B3B2F18AFA721871A2786809@DM5PR03MB3098.namprd03.prod.outlook.com>
References: <DM5PR03MB30987B3B2F18AFA721871A2786809@DM5PR03MB3098.namprd03.prod.outlook.com>
Message-ID: <CAFL1w=5u1GmU39TNZj9Nw84zoeQ5EkR+JAA+qrTX1cUTQUX49w@mail.gmail.com>

Hi Julia,

We have had to deal with this on numerous occasions.  Fortunately, we have
been able to resolve the situation each time with frequent communications
to the customer, but we do have avenues of recourse built into our contract
in the event a situation should escalate.  The first course of action would
be to suspend services.  Typically, the threat of this would be enough to
move things forward.  The next area of recourse would be to turn everything
over to a collection agency.  That would be handled by our Accounts
Receivable Department on campus.  If all else fails, we can also seek legal
action, and it is written into the contract that the customer would also be
responsible for the cost of collections and any legal fees.  Lastly, we do
have a clause in our contract that states the University can apply interest
on a monthly basis if desired.  However, we have not yet gone down that
road.  A broader discussion would first need to be had with our Cost
Accounting group that manages the recharge centers on campus.

Best Regards,

Matt


On Tue, Mar 21, 2023 at 7:35?AM Aebersold, Julia <
julia.aebersold at louisville.edu> wrote:

> Hello everyone.  We have a few external clients that are habitual late
> payers for their invoices.
>
>
>
> How does your facility deal with these late payers?  I?m thinking of
> applying an interest payment after a certain time period similar to credit
> card companies, but I want to hear what others do to encourage clients to
> pay on time.
>
>
>
> Cheers!
>
>
>
> Julia Aebersold, Ph.D.
>
> Manager, Micro/Nano Technology Center
>
> University of Louisville
>
> Shumaker Research Building, Room 233
>
> 2210 South Brook Street
>
> Louisville, KY  40292
>
> (502) 852-1572
>
>
>
> http://louisville.edu/micronano/
>
>
> _______________________________________________
> labnetwork mailing list
> labnetwork at mtl.mit.edu
> https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork
>


-- 

--
Matthew T. Moneck, Ph.D
Executive Director, Claire & John Bertucci Nanotechnology Laboratory
Electrical & Computer Engineering | Carnegie Mellon University
5000 Forbes Avenue, Pittsburgh, PA 15213-3890
Phone: 412-268-5430
ece.cmu.edu
nanofab.ece.cmu.edu
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From joseph.losby at ucalgary.ca  Wed Mar 22 11:47:36 2023
From: joseph.losby at ucalgary.ca (Joseph Losby)
Date: Wed, 22 Mar 2023 15:47:36 +0000
Subject: [labnetwork] Is your facility ISO certified?
Message-ID: <YT1PR01MB871557F65CD3FA67EB432C068E869@YT1PR01MB8715.CANPRD01.PROD.OUTLOOK.COM>

Hello.

Is your cleanroom facility ISO certified?  What are your reasons for having or not having ISO certification?  Are there any particular changes you have had to make to your facility to adhere to standards?

The costs appear to be substantial, and we are still deciding whether or not we should go this route.

Cheers and thanks for your replies,
Joe


Joseph Losby, PhD.
Operations Manager, qLab
Quantum City, University of Calgary
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From jtmitch5 at ncsu.edu  Wed Mar 22 14:29:39 2023
From: jtmitch5 at ncsu.edu (James Mitchell)
Date: Wed, 22 Mar 2023 14:29:39 -0400
Subject: [labnetwork] Suss MA6 Question
Message-ID: <CAEXS_M-9AfbQv1TzikGbZ_tLVdF4hf_O_rVA3Qh7wp2t4vXyKg@mail.gmail.com>

Lamp power supply will not turn on after lamp failure.
We had a lamp (350 W) pop on our system.
Cleaned up and installed a new lamp.
When we start the power supply the breaker in the back of the system trips.
Specifically, it trips when we press CP. System starts at STAND-BY.
Press "ON" and the display shows "READY". Press CP and it displays
"Wait..." for a second and then trips.
We checked for shorts and all looked good. We swapped to the other 220 Volt
plug in the back and it trips as well.
Any ideas on this? We are not sure if the start box or the supply itself is
the issue.


*Thank you, Jim*

*James Mitchell*
*Specialty Trades Technician*
*Dept. of Electrical and Computer Engineering*
*North Carolina State University Nanofabrication Facility (NNF)*
*MRC RM243A **Box 7911*
*2410 Campus Shore Dr., Raleigh, NC 27606*
*jtmitch5 at ncsu.edu* <jtmitch5 at ncsu.edu>
*Desk: 919-515-5394*
*Cell: 919-717-7325*
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From Howard.Northfield at uottawa.ca  Wed Mar 22 15:54:58 2023
From: Howard.Northfield at uottawa.ca (Howard Northfield)
Date: Wed, 22 Mar 2023 19:54:58 +0000
Subject: [labnetwork] Is your facility ISO certified?
In-Reply-To: <YT1PR01MB871557F65CD3FA67EB432C068E869@YT1PR01MB8715.CANPRD01.PROD.OUTLOOK.COM>
References: <YT1PR01MB871557F65CD3FA67EB432C068E869@YT1PR01MB8715.CANPRD01.PROD.OUTLOOK.COM>
Message-ID: <QB1PR01MB3025B5B887F69F91DBA45C719F869@QB1PR01MB3025.CANPRD01.PROD.OUTLOOK.COM>


I believe ISO certification is really only required if you want to do business in Europe.


________________________________
From: labnetwork <labnetwork-bounces at mtl.mit.edu> on behalf of Joseph Losby <joseph.losby at ucalgary.ca>
Sent: Wednesday, March 22, 2023 11:47 AM
To: labnetwork at mtl.mit.edu <labnetwork at mtl.mit.edu>
Subject: [labnetwork] Is your facility ISO certified?

Attention : courriel externe | external email
Hello.

Is your cleanroom facility ISO certified?  What are your reasons for having or not having ISO certification?  Are there any particular changes you have had to make to your facility to adhere to standards?

The costs appear to be substantial, and we are still deciding whether or not we should go this route.

Cheers and thanks for your replies,
Joe


Joseph Losby, PhD.
Operations Manager, qLab
Quantum City, University of Calgary
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From spaolini at cns.fas.harvard.edu  Wed Mar 22 16:47:01 2023
From: spaolini at cns.fas.harvard.edu (Paolini, Steven)
Date: Wed, 22 Mar 2023 20:47:01 +0000
Subject: [labnetwork] Is your facility ISO certified?
In-Reply-To: <YT1PR01MB871557F65CD3FA67EB432C068E869@YT1PR01MB8715.CANPRD01.PROD.OUTLOOK.COM>
References: <YT1PR01MB871557F65CD3FA67EB432C068E869@YT1PR01MB8715.CANPRD01.PROD.OUTLOOK.COM>
Message-ID: <BL0PR07MB40504AD4575368D4F24A9861DF869@BL0PR07MB4050.namprd07.prod.outlook.com>

Joseph,
   ISO certification is primarily for a manufacturing facility. I don't know of any benefit a shared use facility (I'm assuming that's what you have) would gain.
Becoming ISO certified is extremely expensive and disruptive, you must also allow annual "audits" to your facility which again are very expensive and disruptive.
Iso Certification, in simple terms is just an accreditation that you do what you document and document what you do.
I remember confronting the CEO of a company that I used to work for and asking him if it made the facility any better, his answer was a firm "NO".  I then inquired as to why we do it and the answer was "Because our competition has it".
  Best of luck,
   Steve Paolini  Equipment Dood
Harvard University

________________________________
From: labnetwork <labnetwork-bounces at mtl.mit.edu> on behalf of Joseph Losby <joseph.losby at ucalgary.ca>
Sent: Wednesday, March 22, 2023 12:47 PM
To: labnetwork at mtl.mit.edu <labnetwork at mtl.mit.edu>
Subject: [labnetwork] Is your facility ISO certified?

Hello.

Is your cleanroom facility ISO certified?  What are your reasons for having or not having ISO certification?  Are there any particular changes you have had to make to your facility to adhere to standards?

The costs appear to be substantial, and we are still deciding whether or not we should go this route.

Cheers and thanks for your replies,
Joe


Joseph Losby, PhD.
Operations Manager, qLab
Quantum City, University of Calgary
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From julia.aebersold at louisville.edu  Wed Mar 22 17:53:39 2023
From: julia.aebersold at louisville.edu (Aebersold, Julia)
Date: Wed, 22 Mar 2023 21:53:39 +0000
Subject: [labnetwork] Suss MA6 Question
In-Reply-To: <CAEXS_M-9AfbQv1TzikGbZ_tLVdF4hf_O_rVA3Qh7wp2t4vXyKg@mail.gmail.com>
References: <CAEXS_M-9AfbQv1TzikGbZ_tLVdF4hf_O_rVA3Qh7wp2t4vXyKg@mail.gmail.com>
Message-ID: <DM5PR03MB309840FBEC3B43967DB446C386869@DM5PR03MB3098.namprd03.prod.outlook.com>

I would ask Mark Anderson of Aligntech.

Mark Anderson
AlignTech, LLC
802-878-0199
markanderson150 at gmail.com<mailto:markanderson150 at gmail.com>

Cheers!

Julia Aebersold, Ph.D.
Manager, Micro/Nano Technology Center
University of Louisville
Shumaker Research Building, Room 233
2210 South Brook Street
Louisville, KY  40292
(502) 852-1572

http://louisville.edu/micronano/

From: labnetwork <labnetwork-bounces at mtl.mit.edu> On Behalf Of James Mitchell
Sent: Wednesday, March 22, 2023 2:30 PM
To: Fab Network <labnetwork at mtl.mit.edu>
Subject: [labnetwork] Suss MA6 Question

CAUTION: This email originated from outside of our organization. Do not click links, open attachments, or respond unless you recognize the sender's email address and know the contents are safe.
Lamp power supply will not turn on after lamp failure.
We had a lamp (350 W) pop on our system.
Cleaned up and installed a new lamp.
When we start the power supply the breaker in the back of the system trips.
Specifically, it trips when we press CP. System starts at STAND-BY.
Press "ON" and the display shows "READY". Press CP and it displays "Wait..." for a second and then trips.
We checked for shorts and all looked good. We swapped to the other 220 Volt plug in the back and it trips as well.
Any ideas on this? We are not sure if the start box or the supply itself is the issue.


Thank you, Jim

James Mitchell
Specialty Trades Technician
Dept. of Electrical and Computer Engineering
North Carolina State University Nanofabrication Facility (NNF)
MRC RM243A Box 7911
2410 Campus Shore Dr., Raleigh, NC 27606
jtmitch5 at ncsu.edu<mailto:jtmitch5 at ncsu.edu>
Desk: 919-515-5394
Cell: 919-717-7325


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From dave101260 at gmail.com  Wed Mar 22 19:17:13 2023
From: dave101260 at gmail.com (Dave Terry)
Date: Wed, 22 Mar 2023 19:17:13 -0400
Subject: [labnetwork] Suss MA6 Question
In-Reply-To: <CAEXS_M-9AfbQv1TzikGbZ_tLVdF4hf_O_rVA3Qh7wp2t4vXyKg@mail.gmail.com>
References: <CAEXS_M-9AfbQv1TzikGbZ_tLVdF4hf_O_rVA3Qh7wp2t4vXyKg@mail.gmail.com>
Message-ID: <CAF8gEbTGjqfL1HwPioX2v2eu_TCsPPwQNgNFfaF+f-A2O5a51g@mail.gmail.com>

I had a similar issue several years ago, and turned out to be the CB on the
back of the system.

Swapped it out, and all is fine since.



On Wed, Mar 22, 2023 at 3:48 PM James Mitchell <jtmitch5 at ncsu.edu> wrote:

> Lamp power supply will not turn on after lamp failure.
> We had a lamp (350 W) pop on our system.
> Cleaned up and installed a new lamp.
> When we start the power supply the breaker in the back of the system trips.
> Specifically, it trips when we press CP. System starts at STAND-BY.
> Press "ON" and the display shows "READY". Press CP and it displays
> "Wait..." for a second and then trips.
> We checked for shorts and all looked good. We swapped to the other 220
> Volt plug in the back and it trips as well.
> Any ideas on this? We are not sure if the start box or the supply
> itself is the issue.
>
>
> *Thank you, Jim*
>
> *James Mitchell*
> *Specialty Trades Technician*
> *Dept. of Electrical and Computer Engineering*
> *North Carolina State University Nanofabrication Facility (NNF)*
> *MRC RM243A **Box 7911*
> *2410 Campus Shore Dr., Raleigh, NC 27606
> <https://www.google.com/maps/search/2410+Campus+Shore+Dr.,+Raleigh,+NC+27606?entry=gmail&source=g>*
> *jtmitch5 at ncsu.edu* <jtmitch5 at ncsu.edu>
> *Desk: 919-515-5394*
> *Cell: 919-717-7325*
>
>
> _______________________________________________
> labnetwork mailing list
> labnetwork at mtl.mit.edu
> https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork
>
-- 
Best Regards,
Dave Terry
???????????????????
Sent from Gmail Mobile
617 784 7942
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From r.khanna at ucl.ac.uk  Thu Mar 23 07:42:37 2023
From: r.khanna at ucl.ac.uk (Khanna, Rohit)
Date: Thu, 23 Mar 2023 11:42:37 +0000
Subject: [labnetwork] Suss MA6 Question
In-Reply-To: <CAEXS_M-9AfbQv1TzikGbZ_tLVdF4hf_O_rVA3Qh7wp2t4vXyKg@mail.gmail.com>
References: <CAEXS_M-9AfbQv1TzikGbZ_tLVdF4hf_O_rVA3Qh7wp2t4vXyKg@mail.gmail.com>
Message-ID: <VI1PR01MB644654C5B77681F362CD0A1DC3879@VI1PR01MB6446.eurprd01.prod.exchangelabs.com>

Hi Mitchell,
                    Could you put some images of the power supply along with the model number. We had a similar UV lamp power supply failure. I had to change the high power MOSFETS and diodes in the unit along with some PTC inrush current limiter. These lamp drivers are fairly advanced as they constantly monitor the power lamp power and lamp current. I had used the following components to get the supply up and running. Repairing this unit involves disassembling the complete power supply and do board level repairs. These parts were ordered from Mouser Electronics.

494-APT2X61D60J Rectifiers Fast Recovery Epitaxial Diode - D
494-APT5010JVRU2 Discrete Semiconductor Modules Power Module - Mosfet
494-APT80M60J Discrete Semiconductor Modules Power MOSFET - MOS8
821-GBPC3510W Bridge Rectifiers 35A 1000V GLASS PASS WIRE
995-MS32-20010
Inrush Current Limiters 32mm 20ohms 10A INRSH CURR LIMITER
TC4420CPA
MOSFET Driver Low Side, 4.5V-18V supply, 6A peak out, 2.1 Ohm output, DIP-8

Warm Regards
Rohit Khanna
Electronic Test & Measurement Engineer
London Centre for NANO Technology, UCL
Ph:+44-020-76799984
Lab: +44 20 3108 1516
Int Ext: 39984

________________________________
From: labnetwork <labnetwork-bounces at mtl.mit.edu> on behalf of James Mitchell <jtmitch5 at ncsu.edu>
Sent: 22 March 2023 18:29
To: Fab Network <labnetwork at mtl.mit.edu>
Subject: [labnetwork] Suss MA6 Question


? Caution: External sender

Lamp power supply will not turn on after lamp failure.
We had a lamp (350 W) pop on our system.
Cleaned up and installed a new lamp.
When we start the power supply the breaker in the back of the system trips.
Specifically, it trips when we press CP. System starts at STAND-BY.
Press "ON" and the display shows "READY". Press CP and it displays "Wait..." for a second and then trips.
We checked for shorts and all looked good. We swapped to the other 220 Volt plug in the back and it trips as well.
Any ideas on this? We are not sure if the start box or the supply itself is the issue.


Thank you, Jim

James Mitchell
Specialty Trades Technician
Dept. of Electrical and Computer Engineering
North Carolina State University Nanofabrication Facility (NNF)
MRC RM243A Box 7911
2410 Campus Shore Dr., Raleigh, NC 27606
jtmitch5 at ncsu.edu<mailto:jtmitch5 at ncsu.edu>
Desk: 919-515-5394
Cell: 919-717-7325


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From cveith at seas.upenn.edu  Thu Mar 23 07:53:39 2023
From: cveith at seas.upenn.edu (Charles Veith)
Date: Thu, 23 Mar 2023 07:53:39 -0400
Subject: [labnetwork] Is your facility ISO certified?
In-Reply-To: <YT1PR01MB871557F65CD3FA67EB432C068E869@YT1PR01MB8715.CANPRD01.PROD.OUTLOOK.COM>
References: <YT1PR01MB871557F65CD3FA67EB432C068E869@YT1PR01MB8715.CANPRD01.PROD.OUTLOOK.COM>
Message-ID: <CAM0GB=GhipNYSbAa53ZWsWJoLRgxXccV1ieAoqCozRiR=Sg9OA@mail.gmail.com>

Hi Joe
       I might be wrong but the ISO Standards are primarily for
manufacturing facilities. As for a
research lab, I do not believe extra spending and huge increase in
paperwork can not be
justified.
       My recommendation would be to take the 3 day class clean room
protocols and then
implement them. At one point our former Technical Director Noah Clay was
reporting that our
iso quals in the lithography was .5 ISO higher than the room was
rated(There was no adjustment
of air flow to accomplish this). This was totally done through proper
daily/weekly/month cleaning
procedures.

Regards,

Charlie

On Wed, Mar 22, 2023 at 3:51?PM Joseph Losby <joseph.losby at ucalgary.ca>
wrote:

> Hello.
>
> Is your cleanroom facility ISO certified?  What are your reasons for
> having or not having ISO certification?  Are there any particular changes
> you have had to make to your facility to adhere to standards?
>
> The costs appear to be substantial, and we are still deciding whether or
> not we should go this route.
>
> Cheers and thanks for your replies,
> Joe
>
>
> Joseph Losby, PhD.
> Operations Manager, qLab
> Quantum City, University of Calgary
> _______________________________________________
> labnetwork mailing list
> labnetwork at mtl.mit.edu
>
> https://urldefense.com/v3/__https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork__;!!IBzWLUs!UCW6Y2zFatcpANSkj2tMiD--uRnMKLp4zzAWrXFnXCQRdMbfJfc-MVxRmx4x-AtNiwikOZmYBlh3ED-FiZqS2bFq6sfP5A$
>
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From jtmitch5 at ncsu.edu  Thu Mar 23 08:18:18 2023
From: jtmitch5 at ncsu.edu (James Mitchell)
Date: Thu, 23 Mar 2023 08:18:18 -0400
Subject: [labnetwork] Suss MA6 Question
In-Reply-To: <VI1PR01MB644654C5B77681F362CD0A1DC3879@VI1PR01MB6446.eurprd01.prod.exchangelabs.com>
References: <CAEXS_M-9AfbQv1TzikGbZ_tLVdF4hf_O_rVA3Qh7wp2t4vXyKg@mail.gmail.com>
 <VI1PR01MB644654C5B77681F362CD0A1DC3879@VI1PR01MB6446.eurprd01.prod.exchangelabs.com>
Message-ID: <CAEXS_M-sXrRa_4z8MsZH-wh-OGgVHmi99j2uZ+4HH14RQ-_sPQ@mail.gmail.com>

Thanks, we have the CIC1200. Do you have the schematics for this?

[image: 20230323_075350.jpg]

On Thu, Mar 23, 2023 at 7:42?AM Khanna, Rohit <r.khanna at ucl.ac.uk> wrote:

> Hi Mitchell,
>                     Could you put some images of the power supply along
> with the model number. We had a similar UV lamp power supply failure. I had
> to change the high power MOSFETS and diodes in the unit along with some
> PTC inrush current limiter. These lamp drivers are fairly advanced as they
> constantly monitor the power lamp power and lamp current. I had used the
> following components to get the supply up and running. Repairing this unit
> involves disassembling the complete power supply and do board level
> repairs. These parts were ordered from Mouser Electronics.
>
> 494-APT2X61D60J Rectifiers Fast Recovery Epitaxial Diode - D
> 494-APT5010JVRU2 Discrete Semiconductor Modules Power Module - Mosfet 494-APT80M60J
> Discrete Semiconductor Modules Power MOSFET - MOS8
> 821-GBPC3510W Bridge Rectifiers 35A 1000V GLASS PASS WIRE
> 995-MS32-20010
> Inrush Current Limiters 32mm 20ohms 10A INRSH CURR LIMITER TC4420CPA
> MOSFET Driver Low Side, 4.5V-18V supply, 6A peak out, 2.1 Ohm output, DIP-8
>
> Warm Regards
> Rohit Khanna
> Electronic Test & Measurement Engineer
> London Centre for NANO Technology, UCL
> Ph:+44-020-76799984
> Lab: +44 20 3108 1516
> Int Ext: 39984
>
> ------------------------------
> *From:* labnetwork <labnetwork-bounces at mtl.mit.edu> on behalf of James
> Mitchell <jtmitch5 at ncsu.edu>
> *Sent:* 22 March 2023 18:29
> *To:* Fab Network <labnetwork at mtl.mit.edu>
> *Subject:* [labnetwork] Suss MA6 Question
>
>
> ? Caution: External sender
>
> Lamp power supply will not turn on after lamp failure.
> We had a lamp (350 W) pop on our system.
> Cleaned up and installed a new lamp.
> When we start the power supply the breaker in the back of the system trips.
> Specifically, it trips when we press CP. System starts at STAND-BY.
> Press "ON" and the display shows "READY". Press CP and it displays
> "Wait..." for a second and then trips.
> We checked for shorts and all looked good. We swapped to the other 220
> Volt plug in the back and it trips as well.
> Any ideas on this? We are not sure if the start box or the supply
> itself is the issue.
>
>
> *Thank you, Jim*
>
> *James Mitchell*
> *Specialty Trades Technician*
> *Dept. of Electrical and Computer Engineering*
> *North Carolina State University Nanofabrication Facility (NNF)*
> *MRC RM243A **Box 7911*
> *2410 Campus Shore Dr., Raleigh, NC 27606*
> *jtmitch5 at ncsu.edu* <jtmitch5 at ncsu.edu>
> *Desk: 919-515-5394*
> *Cell: 919-717-7325*
>
>
>

-- 
*Thank you, Jim*

*James Mitchell*
*Specialty Trades Technician*
*Dept. of Electrical and Computer Engineering*
*North Carolina State University Nanofabrication Facility (NNF)*
*MRC RM243A **Box 7911*
*2410 Campus Shore Dr., Raleigh, NC 27606*
*jtmitch5 at ncsu.edu* <jtmitch5 at ncsu.edu>
*Desk: 919-515-5394*
*Cell: 919-717-7325*
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From r.khanna at ucl.ac.uk  Thu Mar 23 08:31:49 2023
From: r.khanna at ucl.ac.uk (Khanna, Rohit)
Date: Thu, 23 Mar 2023 12:31:49 +0000
Subject: [labnetwork] Suss MA6 Question
In-Reply-To: <CAEXS_M-sXrRa_4z8MsZH-wh-OGgVHmi99j2uZ+4HH14RQ-_sPQ@mail.gmail.com>
References: <CAEXS_M-9AfbQv1TzikGbZ_tLVdF4hf_O_rVA3Qh7wp2t4vXyKg@mail.gmail.com>
 <VI1PR01MB644654C5B77681F362CD0A1DC3879@VI1PR01MB6446.eurprd01.prod.exchangelabs.com>
 <CAEXS_M-sXrRa_4z8MsZH-wh-OGgVHmi99j2uZ+4HH14RQ-_sPQ@mail.gmail.com>
Message-ID: <VI1PR01MB644652FD91984F97DA56E1C1C3879@VI1PR01MB6446.eurprd01.prod.exchangelabs.com>

Hi James,
                 Our unit was very similar to yours. Unfortunately, it's hard to get the schematics for these, however I can assure you these are very similar, and they are standard buck boost convertor or SEPIC convertors. The MOSFET and diodes are easy to spot as they are mounted on a big heat sink with thermal paste.

Warm Regards
Rohit Khanna
Electronic Test & Measurement Engineer
London Centre for NANO Technology, UCL
Ph:+44-020-76799984
Lab: +44 20 3108 1516
Int Ext: 39984

________________________________
From: James Mitchell <jtmitch5 at ncsu.edu>
Sent: 23 March 2023 12:18
To: Khanna, Rohit <r.khanna at ucl.ac.uk>
Cc: Fab Network <labnetwork at mtl.mit.edu>
Subject: Re: [labnetwork] Suss MA6 Question

Thanks, we have the CIC1200. Do you have the schematics for this?

[20230323_075350.jpg]

On Thu, Mar 23, 2023 at 7:42?AM Khanna, Rohit <r.khanna at ucl.ac.uk<mailto:r.khanna at ucl.ac.uk>> wrote:
Hi Mitchell,
                    Could you put some images of the power supply along with the model number. We had a similar UV lamp power supply failure. I had to change the high power MOSFETS and diodes in the unit along with some PTC inrush current limiter. These lamp drivers are fairly advanced as they constantly monitor the power lamp power and lamp current. I had used the following components to get the supply up and running. Repairing this unit involves disassembling the complete power supply and do board level repairs. These parts were ordered from Mouser Electronics.

494-APT2X61D60J Rectifiers Fast Recovery Epitaxial Diode - D
494-APT5010JVRU2 Discrete Semiconductor Modules Power Module - Mosfet
494-APT80M60J Discrete Semiconductor Modules Power MOSFET - MOS8
821-GBPC3510W Bridge Rectifiers 35A 1000V GLASS PASS WIRE
995-MS32-20010
Inrush Current Limiters 32mm 20ohms 10A INRSH CURR LIMITER
TC4420CPA
MOSFET Driver Low Side, 4.5V-18V supply, 6A peak out, 2.1 Ohm output, DIP-8

Warm Regards
Rohit Khanna
Electronic Test & Measurement Engineer
London Centre for NANO Technology, UCL
Ph:+44-020-76799984
Lab: +44 20 3108 1516
Int Ext: 39984

________________________________
From: labnetwork <labnetwork-bounces at mtl.mit.edu<mailto:labnetwork-bounces at mtl.mit.edu>> on behalf of James Mitchell <jtmitch5 at ncsu.edu<mailto:jtmitch5 at ncsu.edu>>
Sent: 22 March 2023 18:29
To: Fab Network <labnetwork at mtl.mit.edu<mailto:labnetwork at mtl.mit.edu>>
Subject: [labnetwork] Suss MA6 Question


? Caution: External sender

Lamp power supply will not turn on after lamp failure.
We had a lamp (350 W) pop on our system.
Cleaned up and installed a new lamp.
When we start the power supply the breaker in the back of the system trips.
Specifically, it trips when we press CP. System starts at STAND-BY.
Press "ON" and the display shows "READY". Press CP and it displays "Wait..." for a second and then trips.
We checked for shorts and all looked good. We swapped to the other 220 Volt plug in the back and it trips as well.
Any ideas on this? We are not sure if the start box or the supply itself is the issue.


Thank you, Jim

James Mitchell
Specialty Trades Technician
Dept. of Electrical and Computer Engineering
North Carolina State University Nanofabrication Facility (NNF)
MRC RM243A Box 7911
2410 Campus Shore Dr., Raleigh, NC 27606
jtmitch5 at ncsu.edu<mailto:jtmitch5 at ncsu.edu>
Desk: 919-515-5394
Cell: 919-717-7325




--
Thank you, Jim

James Mitchell
Specialty Trades Technician
Dept. of Electrical and Computer Engineering
North Carolina State University Nanofabrication Facility (NNF)
MRC RM243A Box 7911
2410 Campus Shore Dr., Raleigh, NC 27606
jtmitch5 at ncsu.edu<mailto:jtmitch5 at ncsu.edu>
Desk: 919-515-5394
Cell: 919-717-7325


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From jtmitch5 at ncsu.edu  Thu Mar 23 08:50:05 2023
From: jtmitch5 at ncsu.edu (James Mitchell)
Date: Thu, 23 Mar 2023 08:50:05 -0400
Subject: [labnetwork] Suss MA6 Question
In-Reply-To: <CAF8gEbTGjqfL1HwPioX2v2eu_TCsPPwQNgNFfaF+f-A2O5a51g@mail.gmail.com>
References: <CAEXS_M-9AfbQv1TzikGbZ_tLVdF4hf_O_rVA3Qh7wp2t4vXyKg@mail.gmail.com>
 <CAF8gEbTGjqfL1HwPioX2v2eu_TCsPPwQNgNFfaF+f-A2O5a51g@mail.gmail.com>
Message-ID: <CAEXS_M-dtLLPA_M5TEijSeeKmiCBV3VhPhUcosXYbf+BYtjVAA@mail.gmail.com>

Dave, Do you have a part number for CB?
I think I will try this first.

Jim

On Wed, Mar 22, 2023 at 7:17?PM Dave Terry <dave101260 at gmail.com> wrote:

> I had a similar issue several years ago, and turned out to be the CB on
> the back of the system.
>
> Swapped it out, and all is fine since.
>
>
>
> On Wed, Mar 22, 2023 at 3:48 PM James Mitchell <jtmitch5 at ncsu.edu> wrote:
>
>> Lamp power supply will not turn on after lamp failure.
>> We had a lamp (350 W) pop on our system.
>> Cleaned up and installed a new lamp.
>> When we start the power supply the breaker in the back of the system
>> trips.
>> Specifically, it trips when we press CP. System starts at STAND-BY.
>> Press "ON" and the display shows "READY". Press CP and it displays
>> "Wait..." for a second and then trips.
>> We checked for shorts and all looked good. We swapped to the other 220
>> Volt plug in the back and it trips as well.
>> Any ideas on this? We are not sure if the start box or the supply
>> itself is the issue.
>>
>>
>> *Thank you, Jim*
>>
>> *James Mitchell*
>> *Specialty Trades Technician*
>> *Dept. of Electrical and Computer Engineering*
>> *North Carolina State University Nanofabrication Facility (NNF)*
>> *MRC RM243A **Box 7911*
>> *2410 Campus Shore Dr., Raleigh, NC 27606
>> <https://www.google.com/maps/search/2410+Campus+Shore+Dr.,+Raleigh,+NC+27606?entry=gmail&source=g>*
>> *jtmitch5 at ncsu.edu* <jtmitch5 at ncsu.edu>
>> *Desk: 919-515-5394*
>> *Cell: 919-717-7325*
>>
>>
>> _______________________________________________
>> labnetwork mailing list
>> labnetwork at mtl.mit.edu
>> https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork
>>
> --
> Best Regards,
> Dave Terry
> ???????????????????
> Sent from Gmail Mobile
> 617 784 7942
>


-- 
*Thank you, Jim*

*James Mitchell*
*Specialty Trades Technician*
*Dept. of Electrical and Computer Engineering*
*North Carolina State University Nanofabrication Facility (NNF)*
*MRC RM243A **Box 7911*
*2410 Campus Shore Dr., Raleigh, NC 27606*
*jtmitch5 at ncsu.edu* <jtmitch5 at ncsu.edu>
*Desk: 919-515-5394*
*Cell: 919-717-7325*
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From dave101260 at gmail.com  Thu Mar 23 08:52:58 2023
From: dave101260 at gmail.com (Dave Terry)
Date: Thu, 23 Mar 2023 08:52:58 -0400
Subject: [labnetwork] Suss MA6 Question
In-Reply-To: <CAEXS_M-dtLLPA_M5TEijSeeKmiCBV3VhPhUcosXYbf+BYtjVAA@mail.gmail.com>
References: <CAEXS_M-9AfbQv1TzikGbZ_tLVdF4hf_O_rVA3Qh7wp2t4vXyKg@mail.gmail.com>
 <CAF8gEbTGjqfL1HwPioX2v2eu_TCsPPwQNgNFfaF+f-A2O5a51g@mail.gmail.com>
 <CAEXS_M-dtLLPA_M5TEijSeeKmiCBV3VhPhUcosXYbf+BYtjVAA@mail.gmail.com>
Message-ID: <CAF8gEbQFOLOXdh=LwKhywgO00kKCG_-9AyZpdRKCTwB4NoC8rw@mail.gmail.com>

It?ll take me a few to dig it up.

Give me a bit.



On Thu, Mar 23, 2023 at 8:50 AM James Mitchell <jtmitch5 at ncsu.edu> wrote:

> Dave, Do you have a part number for CB?
> I think I will try this first.
>
> Jim
>
> On Wed, Mar 22, 2023 at 7:17?PM Dave Terry <dave101260 at gmail.com> wrote:
>
>> I had a similar issue several years ago, and turned out to be the CB on
>> the back of the system.
>>
>> Swapped it out, and all is fine since.
>>
>>
>>
>> On Wed, Mar 22, 2023 at 3:48 PM James Mitchell <jtmitch5 at ncsu.edu> wrote:
>>
>>> Lamp power supply will not turn on after lamp failure.
>>> We had a lamp (350 W) pop on our system.
>>> Cleaned up and installed a new lamp.
>>> When we start the power supply the breaker in the back of the system
>>> trips.
>>> Specifically, it trips when we press CP. System starts at STAND-BY.
>>> Press "ON" and the display shows "READY". Press CP and it displays
>>> "Wait..." for a second and then trips.
>>> We checked for shorts and all looked good. We swapped to the other 220
>>> Volt plug in the back and it trips as well.
>>> Any ideas on this? We are not sure if the start box or the supply
>>> itself is the issue.
>>>
>>>
>>> *Thank you, Jim*
>>>
>>> *James Mitchell*
>>> *Specialty Trades Technician*
>>> *Dept. of Electrical and Computer Engineering*
>>> *North Carolina State University Nanofabrication Facility (NNF)*
>>> *MRC RM243A **Box 7911*
>>> *2410 Campus Shore Dr., Raleigh, NC 27606
>>> <https://www.google.com/maps/search/2410+Campus+Shore+Dr.,+Raleigh,+NC+27606?entry=gmail&source=g>*
>>> *jtmitch5 at ncsu.edu* <jtmitch5 at ncsu.edu>
>>> *Desk: 919-515-5394*
>>> *Cell: 919-717-7325*
>>>
>>>
>>> _______________________________________________
>>> labnetwork mailing list
>>> labnetwork at mtl.mit.edu
>>> https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork
>>>
>> --
>> Best Regards,
>> Dave Terry
>> ???????????????????
>> Sent from Gmail Mobile
>> 617 784 7942
>>
>
>
> --
> *Thank you, Jim*
>
> *James Mitchell*
> *Specialty Trades Technician*
> *Dept. of Electrical and Computer Engineering*
> *North Carolina State University Nanofabrication Facility (NNF)*
> *MRC RM243A **Box 7911*
> *2410 Campus Shore Dr., Raleigh, NC 27606
> <https://www.google.com/maps/search/2410+Campus+Shore+Dr.,+Raleigh,+NC+27606?entry=gmail&source=g>*
> *jtmitch5 at ncsu.edu* <jtmitch5 at ncsu.edu>
> *Desk: 919-515-5394*
> *Cell: 919-717-7325*
>
>
> --
Best Regards,
Dave Terry
???????????????????
Sent from Gmail Mobile
617 784 7942
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From dave101260 at gmail.com  Thu Mar 23 08:34:11 2023
From: dave101260 at gmail.com (Dave Terry)
Date: Thu, 23 Mar 2023 08:34:11 -0400
Subject: [labnetwork] Suss MA6 Question
In-Reply-To: <CAEXS_M-sXrRa_4z8MsZH-wh-OGgVHmi99j2uZ+4HH14RQ-_sPQ@mail.gmail.com>
References: <CAEXS_M-9AfbQv1TzikGbZ_tLVdF4hf_O_rVA3Qh7wp2t4vXyKg@mail.gmail.com>
 <VI1PR01MB644654C5B77681F362CD0A1DC3879@VI1PR01MB6446.eurprd01.prod.exchangelabs.com>
 <CAEXS_M-sXrRa_4z8MsZH-wh-OGgVHmi99j2uZ+4HH14RQ-_sPQ@mail.gmail.com>
Message-ID: <CAF8gEbR+AXA+ame8yF4mRobc6a9Qei5u3FPMHULKMzCgArh9SA@mail.gmail.com>

I don?t have the prints for the CIC, sorry


On Thu, Mar 23, 2023 at 8:33 AM James Mitchell <jtmitch5 at ncsu.edu> wrote:

> Thanks, we have the CIC1200. Do you have the schematics for this?
>
> [image: 20230323_075350.jpg]
>
> On Thu, Mar 23, 2023 at 7:42?AM Khanna, Rohit <r.khanna at ucl.ac.uk> wrote:
>
>> Hi Mitchell,
>>                     Could you put some images of the power supply along
>> with the model number. We had a similar UV lamp power supply failure. I had
>> to change the high power MOSFETS and diodes in the unit along with some
>> PTC inrush current limiter. These lamp drivers are fairly advanced as they
>> constantly monitor the power lamp power and lamp current. I had used the
>> following components to get the supply up and running. Repairing this unit
>> involves disassembling the complete power supply and do board level
>> repairs. These parts were ordered from Mouser Electronics.
>>
>> 494-APT2X61D60J Rectifiers Fast Recovery Epitaxial Diode - D
>> 494-APT5010JVRU2 Discrete Semiconductor Modules Power Module - Mosfet 494-APT80M60J
>> Discrete Semiconductor Modules Power MOSFET - MOS8
>> 821-GBPC3510W Bridge Rectifiers 35A 1000V GLASS PASS WIRE
>> 995-MS32-20010
>> Inrush Current Limiters 32mm 20ohms 10A INRSH CURR LIMITER TC4420CPA
>> MOSFET Driver Low Side, 4.5V-18V supply, 6A peak out, 2.1 Ohm output,
>> DIP-8
>>
>> Warm Regards
>> Rohit Khanna
>> Electronic Test & Measurement Engineer
>> London Centre for NANO Technology, UCL
>> Ph:+44-020-76799984
>> Lab: +44 20 3108 1516
>> Int Ext: 39984
>>
>> ------------------------------
>> *From:* labnetwork <labnetwork-bounces at mtl.mit.edu> on behalf of James
>> Mitchell <jtmitch5 at ncsu.edu>
>> *Sent:* 22 March 2023 18:29
>> *To:* Fab Network <labnetwork at mtl.mit.edu>
>> *Subject:* [labnetwork] Suss MA6 Question
>>
>>
>> ? Caution: External sender
>>
>> Lamp power supply will not turn on after lamp failure.
>> We had a lamp (350 W) pop on our system.
>> Cleaned up and installed a new lamp.
>> When we start the power supply the breaker in the back of the system
>> trips.
>> Specifically, it trips when we press CP. System starts at STAND-BY.
>> Press "ON" and the display shows "READY". Press CP and it displays
>> "Wait..." for a second and then trips.
>> We checked for shorts and all looked good. We swapped to the other 220
>> Volt plug in the back and it trips as well.
>> Any ideas on this? We are not sure if the start box or the supply
>> itself is the issue.
>>
>>
>> *Thank you, Jim*
>>
>> *James Mitchell*
>> *Specialty Trades Technician*
>> *Dept. of Electrical and Computer Engineering*
>> *North Carolina State University Nanofabrication Facility (NNF)*
>> *MRC RM243A **Box 7911*
>> *2410 Campus Shore Dr., Raleigh, NC 27606
>> <https://www.google.com/maps/search/2410+Campus+Shore+Dr.,+Raleigh,+NC+27606?entry=gmail&source=g>*
>> *jtmitch5 at ncsu.edu* <jtmitch5 at ncsu.edu>
>> *Desk: 919-515-5394*
>> *Cell: 919-717-7325*
>>
>>
>>
>
> --
> *Thank you, Jim*
>
> *James Mitchell*
> *Specialty Trades Technician*
> *Dept. of Electrical and Computer Engineering*
> *North Carolina State University Nanofabrication Facility (NNF)*
> *MRC RM243A **Box 7911*
> *2410 Campus Shore Dr., Raleigh, NC 27606
> <https://www.google.com/maps/search/2410+Campus+Shore+Dr.,+Raleigh,+NC+27606?entry=gmail&source=g>*
> *jtmitch5 at ncsu.edu* <jtmitch5 at ncsu.edu>
> *Desk: 919-515-5394*
> *Cell: 919-717-7325*
>
>
> _______________________________________________
> labnetwork mailing list
> labnetwork at mtl.mit.edu
> https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork
>
-- 
Best Regards,
Dave Terry
???????????????????
Sent from Gmail Mobile
617 784 7942
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From Howard.Northfield at uottawa.ca  Thu Mar 23 09:15:12 2023
From: Howard.Northfield at uottawa.ca (Howard Northfield)
Date: Thu, 23 Mar 2023 13:15:12 +0000
Subject: [labnetwork] Is your facility ISO certified?
In-Reply-To: <BL0PR07MB40504AD4575368D4F24A9861DF869@BL0PR07MB4050.namprd07.prod.outlook.com>
References: <YT1PR01MB871557F65CD3FA67EB432C068E869@YT1PR01MB8715.CANPRD01.PROD.OUTLOOK.COM>
 <BL0PR07MB40504AD4575368D4F24A9861DF869@BL0PR07MB4050.namprd07.prod.outlook.com>
Message-ID: <QB1PR01MB30254D835B49332A3048CEDE9F879@QB1PR01MB3025.CANPRD01.PROD.OUTLOOK.COM>


I was a test ISO auditor at the past Nortel (telecommunications company) during a big push for ISO 9001 certification in the late 1990s, purely to be able to market in Europe.

ISO really only demands a trail of record of internal process, it does not define process details or quality levels.

Howard


________________________________
From: labnetwork <labnetwork-bounces at mtl.mit.edu> on behalf of Paolini, Steven <spaolini at cns.fas.harvard.edu>
Sent: Wednesday, March 22, 2023 4:47 PM
To: Joseph Losby <joseph.losby at ucalgary.ca>; labnetwork at mtl.mit.edu <labnetwork at mtl.mit.edu>
Subject: Re: [labnetwork] Is your facility ISO certified?

Attention : courriel externe | external email
Joseph,
   ISO certification is primarily for a manufacturing facility. I don't know of any benefit a shared use facility (I'm assuming that's what you have) would gain.
Becoming ISO certified is extremely expensive and disruptive, you must also allow annual "audits" to your facility which again are very expensive and disruptive.
Iso Certification, in simple terms is just an accreditation that you do what you document and document what you do.
I remember confronting the CEO of a company that I used to work for and asking him if it made the facility any better, his answer was a firm "NO".  I then inquired as to why we do it and the answer was "Because our competition has it".
  Best of luck,
   Steve Paolini  Equipment Dood
Harvard University

________________________________
From: labnetwork <labnetwork-bounces at mtl.mit.edu> on behalf of Joseph Losby <joseph.losby at ucalgary.ca>
Sent: Wednesday, March 22, 2023 12:47 PM
To: labnetwork at mtl.mit.edu <labnetwork at mtl.mit.edu>
Subject: [labnetwork] Is your facility ISO certified?

Hello.

Is your cleanroom facility ISO certified?  What are your reasons for having or not having ISO certification?  Are there any particular changes you have had to make to your facility to adhere to standards?

The costs appear to be substantial, and we are still deciding whether or not we should go this route.

Cheers and thanks for your replies,
Joe


Joseph Losby, PhD.
Operations Manager, qLab
Quantum City, University of Calgary
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From Peter.Lomax at ed.ac.uk  Thu Mar 23 10:35:40 2023
From: Peter.Lomax at ed.ac.uk (Peter Lomax)
Date: Thu, 23 Mar 2023 14:35:40 +0000
Subject: [labnetwork] Is your facility ISO certified?
In-Reply-To: <BL0PR07MB40504AD4575368D4F24A9861DF869@BL0PR07MB4050.namprd07.prod.outlook.com>
References: <YT1PR01MB871557F65CD3FA67EB432C068E869@YT1PR01MB8715.CANPRD01.PROD.OUTLOOK.COM>
 <BL0PR07MB40504AD4575368D4F24A9861DF869@BL0PR07MB4050.namprd07.prod.outlook.com>
Message-ID: <AS4PR05MB94729D29462FA7D3561CA48CC8879@AS4PR05MB9472.eurprd05.prod.outlook.com>

Hi Joseph,

At SMC in Edinburgh we did consider this but decided it wasn't worth the effort involved for an open access facility.  We do try to have decent systems with good documentation in place and regularly do work for large ISO9000 certified organisations and have always managed to satisfy them with an audit.

Best

Peter

From: labnetwork <labnetwork-bounces at mtl.mit.edu> On Behalf Of Paolini, Steven
Sent: 22 March 2023 20:47
To: Joseph Losby <joseph.losby at ucalgary.ca>; labnetwork at mtl.mit.edu
Subject: Re: [labnetwork] Is your facility ISO certified?

This email was sent to you by someone outside the University.
You should only click on links or attachments if you are certain that the email is genuine and the content is safe.
Joseph,
   ISO certification is primarily for a manufacturing facility. I don't know of any benefit a shared use facility (I'm assuming that's what you have) would gain.
Becoming ISO certified is extremely expensive and disruptive, you must also allow annual "audits" to your facility which again are very expensive and disruptive.
Iso Certification, in simple terms is just an accreditation that you do what you document and document what you do.
I remember confronting the CEO of a company that I used to work for and asking him if it made the facility any better, his answer was a firm "NO".  I then inquired as to why we do it and the answer was "Because our competition has it".
  Best of luck,
   Steve Paolini  Equipment Dood
Harvard University

________________________________
From: labnetwork <labnetwork-bounces at mtl.mit.edu<mailto:labnetwork-bounces at mtl.mit.edu>> on behalf of Joseph Losby <joseph.losby at ucalgary.ca<mailto:joseph.losby at ucalgary.ca>>
Sent: Wednesday, March 22, 2023 12:47 PM
To: labnetwork at mtl.mit.edu<mailto:labnetwork at mtl.mit.edu> <labnetwork at mtl.mit.edu<mailto:labnetwork at mtl.mit.edu>>
Subject: [labnetwork] Is your facility ISO certified?

Hello.

Is your cleanroom facility ISO certified?  What are your reasons for having or not having ISO certification?  Are there any particular changes you have had to make to your facility to adhere to standards?

The costs appear to be substantial, and we are still deciding whether or not we should go this route.

Cheers and thanks for your replies,
Joe


Joseph Losby, PhD.
Operations Manager, qLab
Quantum City, University of Calgary
The University of Edinburgh is a charitable body, registered in Scotland, with registration number SC005336. Is e buidheann carthannais a th' ann an Oilthigh Dh?n ?ideann, cl?raichte an Alba, ?ireamh cl?raidh SC005336.
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From cveith at seas.upenn.edu  Thu Mar 23 11:07:30 2023
From: cveith at seas.upenn.edu (Charles Veith)
Date: Thu, 23 Mar 2023 11:07:30 -0400
Subject: [labnetwork] Is your facility ISO certified?
In-Reply-To: <CAOa6DLW1FLv_LrV9yQF9+WzQtXXJUqwzWrS5YM=vy0X2yAWSjA@mail.gmail.com>
References: <YT1PR01MB871557F65CD3FA67EB432C068E869@YT1PR01MB8715.CANPRD01.PROD.OUTLOOK.COM>
 <CAM0GB=GhipNYSbAa53ZWsWJoLRgxXccV1ieAoqCozRiR=Sg9OA@mail.gmail.com>
 <CAOa6DLW1FLv_LrV9yQF9+WzQtXXJUqwzWrS5YM=vy0X2yAWSjA@mail.gmail.com>
Message-ID: <CAM0GB=HjdjhYxv6gYFopmPJi3fqBXyctGFyg38uqGjgtffcufA@mail.gmail.com>

Hi SamanthaL:
      The organization is called IEST.Org
      Here is the link to the class
      https://www.iest.org/Training-Certs/Contamination-Control-Training
      These are the Certs I would recommend.
      IEST Cleanroom Fundamentals Certificate
     IEST ISO 14644 Fundamentals Certificate
     IEST Cleanroom Operations Certificate
     I have combined the microcontamination and lab
      stockroom (I buy most of the material for the lab for
      many reasons including using high quality materials).
      By merging these two process, I was able to save
      $2.76-$3.76 million over eight years. Which is immediately
      passed on to the users in lower cost, which attracts more
      customers.

Charlie



On Thu, Mar 23, 2023 at 10:50?AM Samantha Roberts <spr26 at cornell.edu> wrote:

> Hello Charles -
>
> My name is Samantha Robert's, I am the new director at the CUNY ASRC
> Nanofab facility.
>
> Could you tell me what 3-day class you were recommending to learn the
> proper protocols?  I would love to register for something similar myself.
>
> Thank you!
>
> Best
> Sam
>
> On Thu, Mar 23, 2023, 8:32 AM Charles Veith <cveith at seas.upenn.edu> wrote:
>
>> Hi Joe
>>        I might be wrong but the ISO Standards are primarily for
>> manufacturing facilities. As for a
>> research lab, I do not believe extra spending and huge increase in
>> paperwork can not be
>> justified.
>>        My recommendation would be to take the 3 day class clean room
>> protocols and then
>> implement them. At one point our former Technical Director Noah Clay was
>> reporting that our
>> iso quals in the lithography was .5 ISO higher than the room was
>> rated(There was no adjustment
>> of air flow to accomplish this). This was totally done through proper
>> daily/weekly/month cleaning
>> procedures.
>>
>> Regards,
>>
>> Charlie
>>
>> On Wed, Mar 22, 2023 at 3:51?PM Joseph Losby <joseph.losby at ucalgary.ca>
>> wrote:
>>
>>> Hello.
>>>
>>> Is your cleanroom facility ISO certified?  What are your reasons for
>>> having or not having ISO certification?  Are there any particular changes
>>> you have had to make to your facility to adhere to standards?
>>>
>>> The costs appear to be substantial, and we are still deciding whether or
>>> not we should go this route.
>>>
>>> Cheers and thanks for your replies,
>>> Joe
>>>
>>>
>>> Joseph Losby, PhD.
>>> Operations Manager, qLab
>>> Quantum City, University of Calgary
>>> _______________________________________________
>>> labnetwork mailing list
>>> labnetwork at mtl.mit.edu
>>>
>>> https://urldefense.com/v3/__https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork__;!!IBzWLUs!UCW6Y2zFatcpANSkj2tMiD--uRnMKLp4zzAWrXFnXCQRdMbfJfc-MVxRmx4x-AtNiwikOZmYBlh3ED-FiZqS2bFq6sfP5A$
>>>
>> _______________________________________________
>> labnetwork mailing list
>> labnetwork at mtl.mit.edu
>> https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork
>> <https://urldefense.com/v3/__https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork__;!!IBzWLUs!QRmim7I9ABKBcPWXWflE9vFzJaHTivd-hnjsBPi3JWcvu1RrtBnYPr2oRQesXwa9ip0HhQ05z2dsuAjLpq0T$>
>>
>
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From tatiana.pinedo at monash.edu  Thu Mar 23 22:09:52 2023
From: tatiana.pinedo at monash.edu (Tatiana Pinedo Rivera)
Date: Fri, 24 Mar 2023 13:09:52 +1100
Subject: [labnetwork] Is your facility ISO certified?
In-Reply-To: <QB1PR01MB30254D835B49332A3048CEDE9F879@QB1PR01MB3025.CANPRD01.PROD.OUTLOOK.COM>
References: <YT1PR01MB871557F65CD3FA67EB432C068E869@YT1PR01MB8715.CANPRD01.PROD.OUTLOOK.COM>
 <BL0PR07MB40504AD4575368D4F24A9861DF869@BL0PR07MB4050.namprd07.prod.outlook.com>
 <QB1PR01MB30254D835B49332A3048CEDE9F879@QB1PR01MB3025.CANPRD01.PROD.OUTLOOK.COM>
Message-ID: <CABQu3YZUgKZ-aY+UBR7xtNGsBZ-ecmDCwSgymPtA=k5o8RzK7A@mail.gmail.com>

Hi Jo and all,

Tatiana Pinedo Rivera from the MCN here (Melbourne, Australia). I am a Team
Lead and a Senior Process Engineer. The Melbourne Centre for
Nanofabrication has been ISO9001 certified for at least roughly 8 years (It
might be more, I am not sure when we started), we also follow the LEAN Six
Sigma methodology and we are not a manufacturing company per say:
In fact, we are an open access nanofab facility, co-funded by the
Australian federal government and the 7 Universities of our State
(Victoria) and the CSIRO. The bulk of our users are academic users
(researchers and their PhD students and postdocs), we train them on our
tools and they do their nanofabrication and research work here but we also
do a substantial amount of fee for service and we also have quite a few
industry clients some of which have their residency in our facility in the
early stages of their startup project.

We have a special affiliation with Monash University as our facility is
technically on Monash campus. Monash University has other Research
Platforms somewhat similar to how we function (such as Monash Micro Imaging
platform, Monash X-Ray Platform, Additive Manufacturing platform etc.) and
they are all ISO9001 as well (more recently than us, I believe).

We at MCN see a lot of benefits from having implemented ISO Platform
Quality Management Systems altogether with LEAN methodology and we do not
think that ISO is only for manufacturing companies. ISO and LEAN is helping
us make sure that we are performing better (more efficiently), continuously
attempting to improve how we do things (safety, trainings, nanofab
processes, tool maintenance, back of the house aspects such as
inventorying of our chemicals and consumables). It helps setting high
quality standards and standardise the processes that can be standardised
(such as our trainings (SOPs, training assessment sheets) and tool
maintenance (Total preventive maintenance schedules and SOPs)). It helps us
keep the cleanroom tidy and things running (we have 5S systems to make sure
everything has a place and we use Kanbans to track our stock of consumables
and chemicals so that we never run out of anything and a the same time we
do not end up buying a surplus of items that we do not need, which helps us
with our sustainability goals too). It makes us more efficient and
consistent, it helps us take better care of the instruments and limit tool
downtime. Ultimately, we have standardised processes and we limit waste of
time, resources and money. Of course it is also a big image aspect
particularly with Industry Clients but academic "clients" also appreciate
the professionalism which translates into better "customer service" too. I
know that one common misconception is that having a quality management
system in place might be too rigid for research and hinder innovation and
creativity, but we do not find this to be true at all.

I am not aware of the specifics of how we started our ISO9001 and LEAN
journey as this happened before I joined MCN. I think we had at that time a
Director that came up with this initiative and made it happen. From what I
have heard, it did require a substantial amount of energy at the beginning
but after a while it runs pretty much (almost) on wheels and we would not
do things otherwise now. Our Engineering and Quality Manager and our
General Manager and Facility Manager help maintain our certifications
up-to-date. They all know far more than me about all the technical aspects
of the certifications we have and how we maintain them. If you would like
me to put you in contact with them, I'll be happy to (Bernie might be
reading us :) as he is on this mailing list)

I hope this is useful.

Tatiana


*Tatiana Pinedo Rivera, PhD* (she/her/hers)
Nanolithography and Characterisation Team Leader
Senior Process Engineer

Melbourne Centre for Nanofabrication
ANFF Victoria
151 Wellington Road, Clayton VIC 3168 Australia

P: +61 (0)3 9905 9660
E: tatiana.pinedo at nanomelbourne.com
W: http://nanomelbourne.com




On Fri, 24 Mar 2023 at 07:24, Howard Northfield <
Howard.Northfield at uottawa.ca> wrote:

>
> I was a test ISO auditor at the past Nortel (telecommunications company)
> during a big push for ISO 9001 certification in the late 1990s, purely to
> be able to market in Europe.
>
> ISO really only demands a trail of record of internal process, it does not
> define process details or quality levels.
>
> Howard
>
>
> ------------------------------
> *From:* labnetwork <labnetwork-bounces at mtl.mit.edu> on behalf of Paolini,
> Steven <spaolini at cns.fas.harvard.edu>
> *Sent:* Wednesday, March 22, 2023 4:47 PM
> *To:* Joseph Losby <joseph.losby at ucalgary.ca>; labnetwork at mtl.mit.edu <
> labnetwork at mtl.mit.edu>
> *Subject:* Re: [labnetwork] Is your facility ISO certified?
>
> *Attention : courriel externe | external email*
> Joseph,
>    ISO certification is primarily for a manufacturing facility. I don't
> know of any benefit a shared use facility (I'm assuming that's what you
> have) would gain.
> Becoming ISO certified is extremely expensive and disruptive, you must
> also allow annual "audits" to your facility which again are very expensive
> and disruptive.
> Iso Certification, in simple terms is just an accreditation that you do
> what you document and document what you do.
> I remember confronting the CEO of a company that I used to work for and
> asking him if it made the facility any better, his answer was a firm "NO".
> I then inquired as to why we do it and the answer was "Because our
> competition has it".
>   Best of luck,
>    Steve Paolini  Equipment Dood
> Harvard University
>
> ------------------------------
> *From:* labnetwork <labnetwork-bounces at mtl.mit.edu> on behalf of Joseph
> Losby <joseph.losby at ucalgary.ca>
> *Sent:* Wednesday, March 22, 2023 12:47 PM
> *To:* labnetwork at mtl.mit.edu <labnetwork at mtl.mit.edu>
> *Subject:* [labnetwork] Is your facility ISO certified?
>
> Hello.
>
> Is your cleanroom facility ISO certified?  What are your reasons for
> having or not having ISO certification?  Are there any particular changes
> you have had to make to your facility to adhere to standards?
>
> The costs appear to be substantial, and we are still deciding whether or
> not we should go this route.
>
> Cheers and thanks for your replies,
> Joe
>
>
> Joseph Losby, PhD.
> Operations Manager, qLab
> Quantum City, University of Calgary
> _______________________________________________
> labnetwork mailing list
> labnetwork at mtl.mit.edu
> https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork
>
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From jhub at dtu.dk  Fri Mar 24 07:58:00 2023
From: jhub at dtu.dk (=?iso-8859-1?Q?J=F6rg_H=FCbner?=)
Date: Fri, 24 Mar 2023 11:58:00 +0000
Subject: [labnetwork] Is your facility ISO certified?
In-Reply-To: <AS4PR05MB94729D29462FA7D3561CA48CC8879@AS4PR05MB9472.eurprd05.prod.outlook.com>
References: <YT1PR01MB871557F65CD3FA67EB432C068E869@YT1PR01MB8715.CANPRD01.PROD.OUTLOOK.COM>
 <BL0PR07MB40504AD4575368D4F24A9861DF869@BL0PR07MB4050.namprd07.prod.outlook.com>
 <AS4PR05MB94729D29462FA7D3561CA48CC8879@AS4PR05MB9472.eurprd05.prod.outlook.com>
Message-ID: <73884611a53043e696e4ffb2b5c34bd1@dtu.dk>

Hi
At DTU Nanolab we have been ISO certified since 2011. The initial effort is quite substantial but keeping it alive actually balances cost and benefit for us. We are an University owned cleanroom with work going from TRL2 to TRL9 (basic research to small scale production). We allow students (B.Sc. to Ph.D.) as well as commercial companies direct access to almost all our tools, of which the majority is also used for small scale production. In order to manage the variety, keep knowledge in house, track changes in procedures etc,  the procedures required to that certification are very useful. Most of all the CAPA  (Corrective And Preventive Action) system is a very useful tool to learn from mistakes and avoid repeating unwanted actions. Also all calibrations, safety procedures, cleaning procedures etc are described, version tracked, verified and sent to hearing to the relevant persons via that system.

We have a smaller number of tools that are classified "research only tool" they are exempt from the certification and are not commonly accessible, often tools that are purchased with initial exclusive use for one specific research project only so you can confine the certification to some of the operation.

Both academic and industrial customers benefit greatly from that system.  Regarding resources: Around 2 FTE's in total, distributed among many engineers and technicians with 0.5 FTE for a Quality Manager. My feeling is that we get more out of it than we put in by preventing mistakes, learning from incidents and keep track of safety procedures, calibrations and preventive maintenance. This is for an operating state, gearing up to a certification from scratch is a another story.

Essentially ISO 9001 is a certification that you get when you can document that you keep what you promise your users/customers. So it also depends what you promise :).

  Best
      J?rg



J?rg H?bner, Ph.D.

 Director

DTU Nanolab
National Center for Nanofabrication and Characterization



Technical University of Denmark

[http://www.dtu.dk/images/DTU_email_logo_01.gif]

DTU Nanolab

?rstedsPlads

Building 347

2800  Kgs Lyngby

Direct   +45 4525 5762
Mobile  +45 22785157

jhub at .dtu.dk<mailto:jhub at .dtu.dk>


www.nanolab.dtu.dk<http://www.nanolab.dtu.dk>






From: labnetwork <labnetwork-bounces at mtl.mit.edu> On Behalf Of Peter Lomax
Sent: 23. marts 2023 15:36
To: Paolini, Steven <spaolini at cns.fas.harvard.edu>; Joseph Losby <joseph.losby at ucalgary.ca>; labnetwork at mtl.mit.edu
Subject: Re: [labnetwork] Is your facility ISO certified?

Hi Joseph,

At SMC in Edinburgh we did consider this but decided it wasn't worth the effort involved for an open access facility.  We do try to have decent systems with good documentation in place and regularly do work for large ISO9000 certified organisations and have always managed to satisfy them with an audit.

Best

Peter

From: labnetwork <labnetwork-bounces at mtl.mit.edu<mailto:labnetwork-bounces at mtl.mit.edu>> On Behalf Of Paolini, Steven
Sent: 22 March 2023 20:47
To: Joseph Losby <joseph.losby at ucalgary.ca<mailto:joseph.losby at ucalgary.ca>>; labnetwork at mtl.mit.edu<mailto:labnetwork at mtl.mit.edu>
Subject: Re: [labnetwork] Is your facility ISO certified?

This email was sent to you by someone outside the University.
You should only click on links or attachments if you are certain that the email is genuine and the content is safe.
Joseph,
   ISO certification is primarily for a manufacturing facility. I don't know of any benefit a shared use facility (I'm assuming that's what you have) would gain.
Becoming ISO certified is extremely expensive and disruptive, you must also allow annual "audits" to your facility which again are very expensive and disruptive.
Iso Certification, in simple terms is just an accreditation that you do what you document and document what you do.
I remember confronting the CEO of a company that I used to work for and asking him if it made the facility any better, his answer was a firm "NO".  I then inquired as to why we do it and the answer was "Because our competition has it".
  Best of luck,
   Steve Paolini  Equipment Dood
Harvard University

________________________________
From: labnetwork <labnetwork-bounces at mtl.mit.edu<mailto:labnetwork-bounces at mtl.mit.edu>> on behalf of Joseph Losby <joseph.losby at ucalgary.ca<mailto:joseph.losby at ucalgary.ca>>
Sent: Wednesday, March 22, 2023 12:47 PM
To: labnetwork at mtl.mit.edu<mailto:labnetwork at mtl.mit.edu> <labnetwork at mtl.mit.edu<mailto:labnetwork at mtl.mit.edu>>
Subject: [labnetwork] Is your facility ISO certified?

Hello.

Is your cleanroom facility ISO certified?  What are your reasons for having or not having ISO certification?  Are there any particular changes you have had to make to your facility to adhere to standards?

The costs appear to be substantial, and we are still deciding whether or not we should go this route.

Cheers and thanks for your replies,
Joe


Joseph Losby, PhD.
Operations Manager, qLab
Quantum City, University of Calgary
The University of Edinburgh is a charitable body, registered in Scotland, with registration number SC005336. Is e buidheann carthannais a th' ann an Oilthigh Dh?n ?ideann, cl?raichte an Alba, ?ireamh cl?raidh SC005336.
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From sturm at princeton.edu  Fri Mar 24 10:48:49 2023
From: sturm at princeton.edu (James C. Sturm)
Date: Fri, 24 Mar 2023 14:48:49 +0000
Subject: [labnetwork] Dry Bed Scrubber for silane, etc
Message-ID: <DM6PR04MB439672E86ED63FDBEB6FFD82BB849@DM6PR04MB4396.namprd04.prod.outlook.com>

We have a Si/Ge UHV CVD system for which we want to purchase a dedicated dry bed scrubber.

Total N2 purges ~38 lpm (from several dry pumps, etc)
Total H2 100 sccm when purging, but normally < 20 sccm
Silane ~2 sccm, Germane <  0.05 sccm,  Diborane and phosphine < 0.01 sccm.
Running < 10 hours a week on average.

We are looking into a Callisto dry bed scrubber (by Jupiter).    We have no experience with such systems, having used a hot "combustion chamber" with air pumped in for 20+ years.

Comments/suggestions/other manufacturers/"been there done that" are welcome.
Thanks,
Jim Sturm and Zoe Cyue, Princeton University

********************************************
Prof. James C. Sturm
     Chair, Department of Electrical and Computer Engineering
     Stephen R. Forrest Professor in Electrical Engineering
     Princeton University
     B210 E-Quad, Olden St.
     Princeton, NJ  08540
     609-258-5610, fax:  609-258-1177
     sturm at princeton.edu<mailto:sturm at princeton.edu>

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From deolivei at ualberta.ca  Fri Mar 24 13:37:04 2023
From: deolivei at ualberta.ca (Gustavo de Oliveira Luiz)
Date: Fri, 24 Mar 2023 11:37:04 -0600
Subject: [labnetwork] Strange "sample memory" with LOR 5B
Message-ID: <CALPuYFzLg-QX5tPGX7qShke=8o75W=xVb_NB0tUYquFskr4FRg@mail.gmail.com>

Hello everyone,

While working on a recipe for LOR 5B/AZ 1512 in our automatic development
system, I encountered some intriguing effects when reusing wafers for my
tests. This could be a problem for our users when developing their own
process, so we'd appreciate it if anyone could help us to understand what
is going on.

Below is a picture of a sample right before exposure, taken using our
MLA150. The dark/bright features you see are NOT etched on the wafer (these
wafers were never etched). The marks are from a previous lithography test.
They become apparent after coating the sample with LOR 5B and even more
after adding AZ 1512. And I don't see them when coating only with AZ 1512
(I reused wafers for that process development without any issues).
[image: Si_w_Oxide_LOR5b-AZ1512_AsCoated.png]
And what is more intriguing is that these features affect
exposure/development of my test mask. For instance, on a virgin sample I
can expose and auto-develop with the same recipe (dose and development
time) I use for the manual process. On a reused sample, the reisst stack
behaves as if it were underexposed (a dose test made this very obvious).

Here are the steps during my tests:

   1. Piranha clean
   2. HMDS prime on a YES oven
   3. Spin-coat with LOR 5B/AZ 1512 (marks show up on a reused sample)
   4. Expose using either a mask aligner or DWL
   5. Auto-develop in our Laurell EDC-650 (resist seems underexposed over
   the marks)
      1. AZ Developer 1:1 ? 90 s
      2. Rinse (DI water) and dry (N2+spin) ? 60-120 s
      3. MF-319 ? 5 s
      4. Rinse (DI water) and dry (N2+spin) ? 60-120 s
   6. Strip resist with Remover PG
   7. Repeat all steps for every iteration

At first I thought that this could actually be some etching of my Si wafers
by MF-319, even though unlikely given the low TMAH concentration (and I'm
not sure why that would affect exposure/development). But the sample in the
image above has 2 ?m thermal oxide, so practically impervious to TMAH. Not
to mention that the brightest crossing marks come from testing a recipe
where TMAH was not used at all. This must be some strange interaction
between LOR 5B and the sample surface, which I'd expect to be practically
reset after piranha and HMDS priming.

My search for more information regarding LOR 5B and it's sensitivity to
surface conditions has proven fruitless so far. And requiring a brand new
sample for every iteration can get expensive quite quickly. We'd appreciate
it if you could point us to some references where this was discussed in any
form, or if you know of a method to avoid this from happening.

I'm sorry for the long email, and thank you in advance for any comments.

Best regards,
--
Gustavo de Oliveira Luiz, PhD
Applications/Research Specialist
nanoFAB, University of Alberta
+1 (780) 619-1463
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From Howard.Northfield at uottawa.ca  Fri Mar 24 14:10:19 2023
From: Howard.Northfield at uottawa.ca (Howard Northfield)
Date: Fri, 24 Mar 2023 18:10:19 +0000
Subject: [labnetwork] Strange "sample memory" with LOR 5B
In-Reply-To: <CALPuYFzLg-QX5tPGX7qShke=8o75W=xVb_NB0tUYquFskr4FRg@mail.gmail.com>
References: <CALPuYFzLg-QX5tPGX7qShke=8o75W=xVb_NB0tUYquFskr4FRg@mail.gmail.com>
Message-ID: <QB1PR01MB302553713D9C0CCAA388A3139F849@QB1PR01MB3025.CANPRD01.PROD.OUTLOOK.COM>


Yes, previous litho leaves "ghosts", I have seen it often.

Howard Northfield
Research Associate
Advanced Research Complex (ARC)
University of Ottawa
________________________________
From: labnetwork <labnetwork-bounces at mtl.mit.edu> on behalf of Gustavo de Oliveira Luiz <deolivei at ualberta.ca>
Sent: Friday, March 24, 2023 1:37 PM
To: labnetwork at mtl.mit.edu <labnetwork at mtl.mit.edu>
Subject: [labnetwork] Strange "sample memory" with LOR 5B

Attention : courriel externe | external email
Hello everyone,

While working on a recipe for LOR 5B/AZ 1512 in our automatic development system, I encountered some intriguing effects when reusing wafers for my tests. This could be a problem for our users when developing their own process, so we'd appreciate it if anyone could help us to understand what is going on.

Below is a picture of a sample right before exposure, taken using our MLA150. The dark/bright features you see are NOT etched on the wafer (these wafers were never etched). The marks are from a previous lithography test. They become apparent after coating the sample with LOR 5B and even more after adding AZ 1512. And I don't see them when coating only with AZ 1512 (I reused wafers for that process development without any issues).
[Si_w_Oxide_LOR5b-AZ1512_AsCoated.png]
And what is more intriguing is that these features affect exposure/development of my test mask. For instance, on a virgin sample I can expose and auto-develop with the same recipe (dose and development time) I use for the manual process. On a reused sample, the reisst stack behaves as if it were underexposed (a dose test made this very obvious).

Here are the steps during my tests:

  1.  Piranha clean
  2.  HMDS prime on a YES oven
  3.  Spin-coat with LOR 5B/AZ 1512 (marks show up on a reused sample)
  4.  Expose using either a mask aligner or DWL
  5.  Auto-develop in our Laurell EDC-650 (resist seems underexposed over the marks)
     *   AZ Developer 1:1 ? 90 s
     *   Rinse (DI water) and dry (N2+spin) ? 60-120 s
     *   MF-319 ? 5 s
     *   Rinse (DI water) and dry (N2+spin) ? 60-120 s
  6.  Strip resist with Remover PG
  7.  Repeat all steps for every iteration

At first I thought that this could actually be some etching of my Si wafers by MF-319, even though unlikely given the low TMAH concentration (and I'm not sure why that would affect exposure/development). But the sample in the image above has 2 ?m thermal oxide, so practically impervious to TMAH. Not to mention that the brightest crossing marks come from testing a recipe where TMAH was not used at all. This must be some strange interaction between LOR 5B and the sample surface, which I'd expect to be practically reset after piranha and HMDS priming.

My search for more information regarding LOR 5B and it's sensitivity to surface conditions has proven fruitless so far. And requiring a brand new sample for every iteration can get expensive quite quickly. We'd appreciate it if you could point us to some references where this was discussed in any form, or if you know of a method to avoid this from happening.

I'm sorry for the long email, and thank you in advance for any comments.

Best regards,
--
Gustavo de Oliveira Luiz, PhD
Applications/Research Specialist
nanoFAB, University of Alberta
+1 (780) 619-1463
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From massey21 at llnl.gov  Fri Mar 24 14:30:20 2023
From: massey21 at llnl.gov (Massey, Travis)
Date: Fri, 24 Mar 2023 18:30:20 +0000
Subject: [labnetwork] Strange "sample memory" with LOR 5B
In-Reply-To: <CALPuYFzLg-QX5tPGX7qShke=8o75W=xVb_NB0tUYquFskr4FRg@mail.gmail.com>
References: <CALPuYFzLg-QX5tPGX7qShke=8o75W=xVb_NB0tUYquFskr4FRg@mail.gmail.com>
Message-ID: <BY5PR09MB544242B473B5C35D39DA3CE3BB849@BY5PR09MB5442.namprd09.prod.outlook.com>

Hi Gustavo,

I don?t have a definitive answer for you, and I?m certainly no chemist, but also consider the role of AZ Developer (another base) and reactions of NMP with residual water or alkaline solutions.

First, the pair of alkaline developers may actually be enough to break through the relatively thin oxide created by the piranha, at which point the bases will start attacking the silicon.  Second, if this is only happening with LOR, it?s also possible that residual liquid (likely alkaline) is being trapped under the AZ 1512 then reacting with the NMP.  Spinning may not do a great job of removing this liquid trapped beneath the resist overhang.  I suspect a bulk attack, though, since the residual patterns in the wafer reflect the resist pattern itself rather than the perimeters of the resist patterns.  I haven?t noticed this before on SiO2, but NMP alone ? and especially water-contaminated NMP ? can attack some metals (Al, Cu, etc.).  This paper suggests that acidic or alkaline contaminants in NMP may exacerbate the problem.  I see these ghosts of previous patterns all the time in aluminum-coated wafers I pattern and reuse repeatedly for process development/characterization, and I?ve recently started seeing it on Ti as well ? no LOR, just an assortment of positive resists.
https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9211805

Best,
Travis Massey
Center for Micro and Nanotechnology
Lawrence Livermore National Laboratory

From: labnetwork <labnetwork-bounces at mtl.mit.edu> On Behalf Of Gustavo de Oliveira Luiz
Sent: Friday, March 24, 2023 10:37 AM
To: labnetwork at mtl.mit.edu
Subject: [labnetwork] Strange "sample memory" with LOR 5B

Hello everyone,

While working on a recipe for LOR 5B/AZ 1512 in our automatic development system, I encountered some intriguing effects when reusing wafers for my tests. This could be a problem for our users when developing their own process, so we'd appreciate it if anyone could help us to understand what is going on.

Below is a picture of a sample right before exposure, taken using our MLA150. The dark/bright features you see are NOT etched on the wafer (these wafers were never etched). The marks are from a previous lithography test. They become apparent after coating the sample with LOR 5B and even more after adding AZ 1512. And I don't see them when coating only with AZ 1512 (I reused wafers for that process development without any issues).
[cid:image001.png at 01D95E44.038894D0]
And what is more intriguing is that these features affect exposure/development of my test mask. For instance, on a virgin sample I can expose and auto-develop with the same recipe (dose and development time) I use for the manual process. On a reused sample, the reisst stack behaves as if it were underexposed (a dose test made this very obvious).

Here are the steps during my tests:

  1.  Piranha clean
  2.  HMDS prime on a YES oven
  3.  Spin-coat with LOR 5B/AZ 1512 (marks show up on a reused sample)
  4.  Expose using either a mask aligner or DWL
  5.  Auto-develop in our Laurell EDC-650 (resist seems underexposed over the marks)

     *   AZ Developer 1:1 ? 90 s
     *   Rinse (DI water) and dry (N2+spin) ? 60-120 s
     *   MF-319 ? 5 s
     *   Rinse (DI water) and dry (N2+spin) ? 60-120 s

  1.  Strip resist with Remover PG
  2.  Repeat all steps for every iteration
At first I thought that this could actually be some etching of my Si wafers by MF-319, even though unlikely given the low TMAH concentration (and I'm not sure why that would affect exposure/development). But the sample in the image above has 2 ?m thermal oxide, so practically impervious to TMAH. Not to mention that the brightest crossing marks come from testing a recipe where TMAH was not used at all. This must be some strange interaction between LOR 5B and the sample surface, which I'd expect to be practically reset after piranha and HMDS priming.

My search for more information regarding LOR 5B and it's sensitivity to surface conditions has proven fruitless so far. And requiring a brand new sample for every iteration can get expensive quite quickly. We'd appreciate it if you could point us to some references where this was discussed in any form, or if you know of a method to avoid this from happening.

I'm sorry for the long email, and thank you in advance for any comments.

Best regards,
--
Gustavo de Oliveira Luiz, PhD
Applications/Research Specialist
nanoFAB, University of Alberta
+1 (780) 619-1463
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From deonc69 at illinois.edu  Fri Mar 24 14:33:37 2023
From: deonc69 at illinois.edu (Collins, Deon)
Date: Fri, 24 Mar 2023 18:33:37 +0000
Subject: [labnetwork] Dry Bed Scrubber for silane, etc
In-Reply-To: <DM6PR04MB439672E86ED63FDBEB6FFD82BB849@DM6PR04MB4396.namprd04.prod.outlook.com>
References: <DM6PR04MB439672E86ED63FDBEB6FFD82BB849@DM6PR04MB4396.namprd04.prod.outlook.com>
Message-ID: <DM6PR11MB31626F29E33FF8CCAC0F4D29D7849@DM6PR11MB3162.namprd11.prod.outlook.com>

Contact Critical Systems Inc. or BAZM. They both have these systems. CS Clean Solutions also offers dry bed systems.

Deon D. Collins

FACILITY MANAGER
Holonyak Lab
University of Illinois at Urbana-Champaign
208 N Wright St Rm. 248 | 2250
Urbana, IL 61801
217-300-7531 | deonc69 at illinois.edu<mailto:deonc69 at illinois.edu>


[cid:image001.png at 01D95E55.3BC66870]<http://illinois.edu/>

Under the Illinois Freedom of Information Act any written communication to or from university employees regarding university business is a public record and may be subject to public disclosure.

Life is not about watching other people live it. It's about you living your own!

From: labnetwork <labnetwork-bounces at mtl.mit.edu> On Behalf Of James C. Sturm
Sent: Friday, March 24, 2023 9:49 AM
To: labnetwork at mtl.mit.edu
Subject: [labnetwork] Dry Bed Scrubber for silane, etc

We have a Si/Ge UHV CVD system for which we want to purchase a dedicated dry bed scrubber.

Total N2 purges ~38 lpm (from several dry pumps, etc)
Total H2 100 sccm when purging, but normally < 20 sccm
Silane ~2 sccm, Germane <  0.05 sccm,  Diborane and phosphine < 0.01 sccm.
Running < 10 hours a week on average.

We are looking into a Callisto dry bed scrubber (by Jupiter).    We have no experience with such systems, having used a hot "combustion chamber" with air pumped in for 20+ years.

Comments/suggestions/other manufacturers/"been there done that" are welcome.
Thanks,
Jim Sturm and Zoe Cyue, Princeton University

********************************************
Prof. James C. Sturm
     Chair, Department of Electrical and Computer Engineering
     Stephen R. Forrest Professor in Electrical Engineering
     Princeton University
     B210 E-Quad, Olden St.
     Princeton, NJ  08540
     609-258-5610, fax:  609-258-1177
     sturm at princeton.edu<mailto:sturm at princeton.edu>

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From spaolini at cns.fas.harvard.edu  Fri Mar 24 16:05:46 2023
From: spaolini at cns.fas.harvard.edu (Paolini, Steven)
Date: Fri, 24 Mar 2023 20:05:46 +0000
Subject: [labnetwork] Dry Bed Scrubber for silane, etc
In-Reply-To: <DM6PR04MB439672E86ED63FDBEB6FFD82BB849@DM6PR04MB4396.namprd04.prod.outlook.com>
References: <DM6PR04MB439672E86ED63FDBEB6FFD82BB849@DM6PR04MB4396.namprd04.prod.outlook.com>
Message-ID: <BL0PR07MB4050F4CE30AB17CB79CCF26BDF849@BL0PR07MB4050.namprd07.prod.outlook.com>

James,
   I would highly recommend a dry bed scrubber for a number of reasons.
Electrical consumption will be seriously reduced since you are not keeping a large mass of "burn box" at elevated temperatures.
If your present unit is of the "burn/wash" type, city water consumption will be eliminated.
I have installed a dual Calisto system for our LPCVD systems and I am quite satisfied with it's performance and features. One outstanding feature is the built in TGMS sensor that will alert you to when the dry bed has reached its lifespan. Most other abatement systems simply monitor exhaust pressure as a trouble indicator. The dual Calisto will not only alert you of a dry bed (cannister) failure, it will automatically switch over to the second canister and you have the luxury of changing the spent one when you have the time.
   Hope this helps,
    Equipment Dood.

Steve Paolini
Principal Equipment Engineer
Harvard University Center for Nanoscale Systems
11 Oxford St.
Cambridge, MA 02138
617- 496- 9816
spaolini at cns.fas.harvard.edu
www.cns.fas.harvard.edu

From: labnetwork <labnetwork-bounces at mtl.mit.edu> On Behalf Of James C. Sturm
Sent: Friday, March 24, 2023 10:49 AM
To: labnetwork at mtl.mit.edu
Subject: [labnetwork] Dry Bed Scrubber for silane, etc

We have a Si/Ge UHV CVD system for which we want to purchase a dedicated dry bed scrubber.

Total N2 purges ~38 lpm (from several dry pumps, etc)
Total H2 100 sccm when purging, but normally < 20 sccm
Silane ~2 sccm, Germane <  0.05 sccm,  Diborane and phosphine < 0.01 sccm.
Running < 10 hours a week on average.

We are looking into a Callisto dry bed scrubber (by Jupiter).    We have no experience with such systems, having used a hot "combustion chamber" with air pumped in for 20+ years.

Comments/suggestions/other manufacturers/"been there done that" are welcome.
Thanks,
Jim Sturm and Zoe Cyue, Princeton University

********************************************
Prof. James C. Sturm
     Chair, Department of Electrical and Computer Engineering
     Stephen R. Forrest Professor in Electrical Engineering
     Princeton University
     B210 E-Quad, Olden St.
     Princeton, NJ  08540
     609-258-5610, fax:  609-258-1177
     sturm at princeton.edu<mailto:sturm at princeton.edu>

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From hollingshead.19 at osu.edu  Fri Mar 24 17:12:57 2023
From: hollingshead.19 at osu.edu (Hollingshead, Dave)
Date: Fri, 24 Mar 2023 21:12:57 +0000
Subject: [labnetwork] Strange "sample memory" with LOR 5B
In-Reply-To: <QB1PR01MB302553713D9C0CCAA388A3139F849@QB1PR01MB3025.CANPRD01.PROD.OUTLOOK.COM>
References: <CALPuYFzLg-QX5tPGX7qShke=8o75W=xVb_NB0tUYquFskr4FRg@mail.gmail.com>
 <QB1PR01MB302553713D9C0CCAA388A3139F849@QB1PR01MB3025.CANPRD01.PROD.OUTLOOK.COM>
Message-ID: <SA1PR01MB6544ED4A152B84375C04F9D1F3849@SA1PR01MB6544.prod.exchangelabs.com>

Hi Gustavo,

We?ve seen ghosting before, although as you mention it has usually been caused by mild etching of the substrate in the developer. Based on your comments I wouldn?t count out something else in this case.

This reminds me of some strange behavior we have seen in some of our nLOF processes done on our MLA. We are still trying to investigate what is happening, but we get odd residue or material adhesion issues on reworked samples. One working theory is that the high power density of the MLA laser exposure is either locally heating the resist to the point of excessive cross-linking or somehow modifying the surface during exposure. Microchem has a white paper that seems to lend some credence to this theory (https://www.microchemicals.com/technical_information/exposure_photoresist.pdf, see page 10).

Any chance you have tried (or could try) repeating the process using a contact aligner on the same substrate and see if you still get the same exposure? If it is an MLA-exclusive issue that would be very interested to know and investigate further.

-Dave
Dave Hollingshead
Manager, Research Operations

The Ohio State University
Nanotech West Labs
Suite 100, 1381 Kinnear Rd, Columbus, OH 43212
614.292.1355 Office
hollingshead.19 at osu.edu<mailto:hollingshead.19 at osu.edu> / nanotech.osu.edu<http://nanotech.osu.edu>

Pronouns: he/him/his



From: labnetwork <labnetwork-bounces at mtl.mit.edu> On Behalf Of Howard Northfield
Sent: Friday, March 24, 2023 14:10
To: Gustavo de Oliveira Luiz <deolivei at ualberta.ca>; labnetwork at mtl.mit.edu
Subject: Re: [labnetwork] Strange "sample memory" with LOR 5B

Yes, previous litho leaves "ghosts", I have seen it often. Howard Northfield Research Associate Advanced Research Complex (ARC) University of Ottawa From: labnetwork <labnetwork-bounces@?mtl.?mit.?edu> on behalf of Gustavo de Oliveira


Yes, previous litho leaves "ghosts", I have seen it often.

Howard Northfield
Research Associate
Advanced Research Complex (ARC)
University of Ottawa
________________________________
From: labnetwork <labnetwork-bounces at mtl.mit.edu<mailto:labnetwork-bounces at mtl.mit.edu>> on behalf of Gustavo de Oliveira Luiz <deolivei at ualberta.ca<mailto:deolivei at ualberta.ca>>
Sent: Friday, March 24, 2023 1:37 PM
To: labnetwork at mtl.mit.edu<mailto:labnetwork at mtl.mit.edu> <labnetwork at mtl.mit.edu<mailto:labnetwork at mtl.mit.edu>>
Subject: [labnetwork] Strange "sample memory" with LOR 5B

Attention : courriel externe | external email
Hello everyone,

While working on a recipe for LOR 5B/AZ 1512 in our automatic development system, I encountered some intriguing effects when reusing wafers for my tests. This could be a problem for our users when developing their own process, so we'd appreciate it if anyone could help us to understand what is going on.

Below is a picture of a sample right before exposure, taken using our MLA150. The dark/bright features you see are NOT etched on the wafer (these wafers were never etched). The marks are from a previous lithography test. They become apparent after coating the sample with LOR 5B and even more after adding AZ 1512. And I don't see them when coating only with AZ 1512 (I reused wafers for that process development without any issues).
[cid:image001.png at 01D95E73.1F416650]
And what is more intriguing is that these features affect exposure/development of my test mask. For instance, on a virgin sample I can expose and auto-develop with the same recipe (dose and development time) I use for the manual process. On a reused sample, the reisst stack behaves as if it were underexposed (a dose test made this very obvious).

Here are the steps during my tests:

  1.  Piranha clean
  2.  HMDS prime on a YES oven
  3.  Spin-coat with LOR 5B/AZ 1512 (marks show up on a reused sample)
  4.  Expose using either a mask aligner or DWL
  5.  Auto-develop in our Laurell EDC-650 (resist seems underexposed over the marks)

     *   AZ Developer 1:1 ? 90 s
     *   Rinse (DI water) and dry (N2+spin) ? 60-120 s
     *   MF-319 ? 5 s
     *   Rinse (DI water) and dry (N2+spin) ? 60-120 s

  1.  Strip resist with Remover PG
  2.  Repeat all steps for every iteration
At first I thought that this could actually be some etching of my Si wafers by MF-319, even though unlikely given the low TMAH concentration (and I'm not sure why that would affect exposure/development). But the sample in the image above has 2 ?m thermal oxide, so practically impervious to TMAH. Not to mention that the brightest crossing marks come from testing a recipe where TMAH was not used at all. This must be some strange interaction between LOR 5B and the sample surface, which I'd expect to be practically reset after piranha and HMDS priming.

My search for more information regarding LOR 5B and it's sensitivity to surface conditions has proven fruitless so far. And requiring a brand new sample for every iteration can get expensive quite quickly. We'd appreciate it if you could point us to some references where this was discussed in any form, or if you know of a method to avoid this from happening.

I'm sorry for the long email, and thank you in advance for any comments.

Best regards,
--
Gustavo de Oliveira Luiz, PhD
Applications/Research Specialist
nanoFAB, University of Alberta
+1 (780) 619-1463
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From hathaway at cns.fas.harvard.edu  Fri Mar 24 17:21:44 2023
From: hathaway at cns.fas.harvard.edu (Hathaway, Malcolm R)
Date: Fri, 24 Mar 2023 21:21:44 +0000
Subject: [labnetwork] Strange "sample memory" with LOR 5B
In-Reply-To: <BY5PR09MB544242B473B5C35D39DA3CE3BB849@BY5PR09MB5442.namprd09.prod.outlook.com>
References: <CALPuYFzLg-QX5tPGX7qShke=8o75W=xVb_NB0tUYquFskr4FRg@mail.gmail.com>
 <BY5PR09MB544242B473B5C35D39DA3CE3BB849@BY5PR09MB5442.namprd09.prod.outlook.com>
Message-ID: <MN2PR07MB6526DCA749B93665FC11C500CB849@MN2PR07MB6526.namprd07.prod.outlook.com>

Hi Gustavo,

Another thought (from a non-photo-expert, for sure!):

It may be the prior photo steps are changing the reflectivity of the silicon (or aluminum, on Travis's samples), especially as it shows up as having an effect on dose.  Surface roughening?  A very thin chemical residue?

Perhaps an AFM scan would be revealing...


Mac Hathaway
Harvard CNS

________________________________
From: labnetwork <labnetwork-bounces at mtl.mit.edu> on behalf of Massey, Travis <massey21 at llnl.gov>
Sent: Friday, March 24, 2023 2:30 PM
To: Gustavo de Oliveira Luiz <deolivei at ualberta.ca>; labnetwork at mtl.mit.edu <labnetwork at mtl.mit.edu>
Subject: Re: [labnetwork] Strange "sample memory" with LOR 5B


Hi Gustavo,



I don?t have a definitive answer for you, and I?m certainly no chemist, but also consider the role of AZ Developer (another base) and reactions of NMP with residual water or alkaline solutions.



First, the pair of alkaline developers may actually be enough to break through the relatively thin oxide created by the piranha, at which point the bases will start attacking the silicon.  Second, if this is only happening with LOR, it?s also possible that residual liquid (likely alkaline) is being trapped under the AZ 1512 then reacting with the NMP.  Spinning may not do a great job of removing this liquid trapped beneath the resist overhang.  I suspect a bulk attack, though, since the residual patterns in the wafer reflect the resist pattern itself rather than the perimeters of the resist patterns.  I haven?t noticed this before on SiO2, but NMP alone ? and especially water-contaminated NMP ? can attack some metals (Al, Cu, etc.).  This paper suggests that acidic or alkaline contaminants in NMP may exacerbate the problem.  I see these ghosts of previous patterns all the time in aluminum-coated wafers I pattern and reuse repeatedly for process development/characterization, and I?ve recently started seeing it on Ti as well ? no LOR, just an assortment of positive resists.

https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9211805<https://urldefense.proofpoint.com/v2/url?u=https-3A__ieeexplore.ieee.org_stamp_stamp.jsp-3Ftp-3D-26arnumber-3D9211805&d=DwMGaQ&c=WO-RGvefibhHBZq3fL85hQ&r=TEMLD8-VsxCGtcVzmvpT5GFNSczskEKHzW6aYlttmIY&m=1-k7qvkCMYMPtYpozWsK_KGAJGieHTpEbECqW_3lIM8S9M8eXG8-e5DadL6e-7pS&s=Z-bdFigBPa6X1HeTz5-YGnfzpYQPP0zbhVFxbzVW_0A&e=>



Best,

Travis Massey

Center for Micro and Nanotechnology

Lawrence Livermore National Laboratory



From: labnetwork <labnetwork-bounces at mtl.mit.edu> On Behalf Of Gustavo de Oliveira Luiz
Sent: Friday, March 24, 2023 10:37 AM
To: labnetwork at mtl.mit.edu
Subject: [labnetwork] Strange "sample memory" with LOR 5B



Hello everyone,



While working on a recipe for LOR 5B/AZ 1512 in our automatic development system, I encountered some intriguing effects when reusing wafers for my tests. This could be a problem for our users when developing their own process, so we'd appreciate it if anyone could help us to understand what is going on.



Below is a picture of a sample right before exposure, taken using our MLA150. The dark/bright features you see are NOT etched on the wafer (these wafers were never etched). The marks are from a previous lithography test. They become apparent after coating the sample with LOR 5B and even more after adding AZ 1512. And I don't see them when coating only with AZ 1512 (I reused wafers for that process development without any issues).

[cid:image001.png at 01D95E44.038894D0]

And what is more intriguing is that these features affect exposure/development of my test mask. For instance, on a virgin sample I can expose and auto-develop with the same recipe (dose and development time) I use for the manual process. On a reused sample, the reisst stack behaves as if it were underexposed (a dose test made this very obvious).



Here are the steps during my tests:

  1.  Piranha clean
  2.  HMDS prime on a YES oven
  3.  Spin-coat with LOR 5B/AZ 1512 (marks show up on a reused sample)
  4.  Expose using either a mask aligner or DWL
  5.  Auto-develop in our Laurell EDC-650 (resist seems underexposed over the marks)

     *   AZ Developer 1:1 ? 90 s
     *   Rinse (DI water) and dry (N2+spin) ? 60-120 s
     *   MF-319 ? 5 s
     *   Rinse (DI water) and dry (N2+spin) ? 60-120 s

  1.  Strip resist with Remover PG
  2.  Repeat all steps for every iteration

At first I thought that this could actually be some etching of my Si wafers by MF-319, even though unlikely given the low TMAH concentration (and I'm not sure why that would affect exposure/development). But the sample in the image above has 2 ?m thermal oxide, so practically impervious to TMAH. Not to mention that the brightest crossing marks come from testing a recipe where TMAH was not used at all. This must be some strange interaction between LOR 5B and the sample surface, which I'd expect to be practically reset after piranha and HMDS priming.



My search for more information regarding LOR 5B and it's sensitivity to surface conditions has proven fruitless so far. And requiring a brand new sample for every iteration can get expensive quite quickly. We'd appreciate it if you could point us to some references where this was discussed in any form, or if you know of a method to avoid this from happening.



I'm sorry for the long email, and thank you in advance for any comments.



Best regards,

--
Gustavo de Oliveira Luiz, PhD
Applications/Research Specialist
nanoFAB, University of Alberta
+1 (780) 619-1463
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From deolivei at ualberta.ca  Fri Mar 24 17:57:16 2023
From: deolivei at ualberta.ca (Gustavo de Oliveira Luiz)
Date: Fri, 24 Mar 2023 15:57:16 -0600
Subject: [labnetwork] Strange "sample memory" with LOR 5B
In-Reply-To: <MN2PR07MB6526DCA749B93665FC11C500CB849@MN2PR07MB6526.namprd07.prod.outlook.com>
References: <CALPuYFzLg-QX5tPGX7qShke=8o75W=xVb_NB0tUYquFskr4FRg@mail.gmail.com>
 <BY5PR09MB544242B473B5C35D39DA3CE3BB849@BY5PR09MB5442.namprd09.prod.outlook.com>
 <MN2PR07MB6526DCA749B93665FC11C500CB849@MN2PR07MB6526.namprd07.prod.outlook.com>
Message-ID: <CALPuYFz9Y4TnP6WupwyCkR4Xgb7Rijczhibd7y_MVJnChTa4rw@mail.gmail.com>

Hi everyone,

First of all, thank you for the comments so far. If anyone else has more
information or suggestions about this, please keep them coming. I just
wanted to clarify some things and add a bit more detail on this issue.

Travis Massey mentioned one thing that caught my attention, which was the
etching at the rims of the mask patterns, where developer may have been
trapped at after the undercut step with MF-319. Indeed, I observed this
kind of thing on a Si (no oxide) wafer where I measured up to a few 100 nm
trenches following the edges of my mask pattern. However this was very
sparse throughout the wafer, while the marks I've shown cover the whole
surface and I could not find anything correlating to this large scale
effect (I used our optical profilometer for this). But interesting that
liquid being trapped under the overhang of a lift-off mask can cause this,
which means we need to be more careful with the rinse steps.

Dave Hollingshead suggested the MLA150 laser causing surface modifications.
Unfortunately I had the same issues when working with a contact aligner, so
I guess that this is not the case.

Malcom Hathaway suggested a change in the substrate reflectivity, which is
my current hypothesis. However this seems to affect both Si and oxide,
since I see this effect on both cases, so this may be in fact a case of
chemicals sticking to the surface and not coming out even during long
piranha baths. I have AFM and other surface characterization options
planned, it is a matter of finding a good time to have it done now.

Thank you all again for the suggestions and references. I'll make sure to
post an update here if I have anything useful.

Best,
--
Gustavo de Oliveira Luiz, PhD
Applications/Research Specialist
nanoFAB, University of Alberta

On Fri, Mar 24, 2023 at 3:21?PM Hathaway, Malcolm R <
hathaway at cns.fas.harvard.edu> wrote:

> Hi Gustavo,
>
> Another thought (from a non-photo-expert, for sure!):
>
> It may be the prior photo steps are changing the reflectivity of the
> silicon (or aluminum, on Travis's samples), especially as it shows up as
> having an effect on dose.  Surface roughening?  A very thin chemical
> residue?
>
> Perhaps an AFM scan would be revealing...
>
>
> Mac Hathaway
> Harvard CNS
>
> ------------------------------
> *From:* labnetwork <labnetwork-bounces at mtl.mit.edu> on behalf of Massey,
> Travis <massey21 at llnl.gov>
> *Sent:* Friday, March 24, 2023 2:30 PM
> *To:* Gustavo de Oliveira Luiz <deolivei at ualberta.ca>;
> labnetwork at mtl.mit.edu <labnetwork at mtl.mit.edu>
> *Subject:* Re: [labnetwork] Strange "sample memory" with LOR 5B
>
>
> Hi Gustavo,
>
>
>
> I don?t have a definitive answer for you, and I?m certainly no chemist,
> but also consider the role of AZ Developer (another base) and reactions of
> NMP with residual water or alkaline solutions.
>
>
>
> First, the pair of alkaline developers *may* actually be enough to break
> through the relatively thin oxide created by the piranha, at which point
> the bases will start attacking the silicon.  Second, if this is only
> happening with LOR, it?s also possible that residual liquid (likely
> alkaline) is being trapped under the AZ 1512 then reacting with the NMP.
> Spinning may not do a great job of removing this liquid trapped beneath the
> resist overhang.  I suspect a bulk attack, though, since the residual
> patterns in the wafer reflect the resist pattern itself rather than the
> perimeters of the resist patterns.  I haven?t noticed this before on SiO2,
> but NMP alone ? and especially water-contaminated NMP ? can attack some
> metals (Al, Cu, etc.).  This paper suggests that acidic or alkaline
> contaminants in NMP may exacerbate the problem.  I see these ghosts of
> previous patterns all the time in aluminum-coated wafers I pattern and
> reuse repeatedly for process development/characterization, and I?ve
> recently started seeing it on Ti as well ? no LOR, just an assortment of
> positive resists.
>
> https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9211805
> <https://urldefense.proofpoint.com/v2/url?u=https-3A__ieeexplore.ieee.org_stamp_stamp.jsp-3Ftp-3D-26arnumber-3D9211805&d=DwMGaQ&c=WO-RGvefibhHBZq3fL85hQ&r=TEMLD8-VsxCGtcVzmvpT5GFNSczskEKHzW6aYlttmIY&m=1-k7qvkCMYMPtYpozWsK_KGAJGieHTpEbECqW_3lIM8S9M8eXG8-e5DadL6e-7pS&s=Z-bdFigBPa6X1HeTz5-YGnfzpYQPP0zbhVFxbzVW_0A&e=>
>
>
>
> Best,
>
> Travis Massey
>
> Center for Micro and Nanotechnology
>
> Lawrence Livermore National Laboratory
>
>
>
> *From:* labnetwork <labnetwork-bounces at mtl.mit.edu> * On Behalf Of *Gustavo
> de Oliveira Luiz
> *Sent:* Friday, March 24, 2023 10:37 AM
> *To:* labnetwork at mtl.mit.edu
> *Subject:* [labnetwork] Strange "sample memory" with LOR 5B
>
>
>
> Hello everyone,
>
>
>
> While working on a recipe for LOR 5B/AZ 1512 in our automatic development
> system, I encountered some intriguing effects when reusing wafers for my
> tests. This could be a problem for our users when developing their own
> process, so we'd appreciate it if anyone could help us to understand what
> is going on.
>
>
>
> Below is a picture of a sample right before exposure, taken using our
> MLA150. The dark/bright features you see are NOT etched on the wafer (these
> wafers were never etched). The marks are from a previous lithography test.
> They become apparent after coating the sample with LOR 5B and even more
> after adding AZ 1512. And I don't see them when coating only with AZ 1512
> (I reused wafers for that process development without any issues).
>
> And what is more intriguing is that these features affect
> exposure/development of my test mask. For instance, on a virgin sample I
> can expose and auto-develop with the same recipe (dose and development
> time) I use for the manual process. On a reused sample, the reisst stack
> behaves as if it were underexposed (a dose test made this very obvious).
>
>
>
> Here are the steps during my tests:
>
>    1. Piranha clean
>    2. HMDS prime on a YES oven
>    3. Spin-coat with LOR 5B/AZ 1512 (marks show up on a reused sample)
>    4. Expose using either a mask aligner or DWL
>    5. Auto-develop in our Laurell EDC-650 (resist seems underexposed over
>    the marks)
>
>
>    1. AZ Developer 1:1 ? 90 s
>       2. Rinse (DI water) and dry (N2+spin) ? 60-120 s
>       3. MF-319 ? 5 s
>       4. Rinse (DI water) and dry (N2+spin) ? 60-120 s
>
>
>    1. Strip resist with Remover PG
>    2. Repeat all steps for every iteration
>
> At first I thought that this could actually be some etching of my Si
> wafers by MF-319, even though unlikely given the low TMAH concentration
> (and I'm not sure why that would affect exposure/development). But the
> sample in the image above has 2 ?m thermal oxide, so practically impervious
> to TMAH. Not to mention that the brightest crossing marks come from testing
> a recipe where TMAH was not used at all. This must be some strange
> interaction between LOR 5B and the sample surface, which I'd expect to be
> practically reset after piranha and HMDS priming.
>
>
>
> My search for more information regarding LOR 5B and it's sensitivity to
> surface conditions has proven fruitless so far. And requiring a brand new
> sample for every iteration can get expensive quite quickly. We'd appreciate
> it if you could point us to some references where this was discussed in any
> form, or if you know of a method to avoid this from happening.
>
>
>
> I'm sorry for the long email, and thank you in advance for any comments.
>
>
>
> Best regards,
>
> --
> Gustavo de Oliveira Luiz, PhD
> Applications/Research Specialist
> nanoFAB, University of Alberta
> +1 (780) 619-1463
>
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From dlloyd at laseroptical.co.uk  Mon Mar 27 04:27:51 2023
From: dlloyd at laseroptical.co.uk (Daniel Lloyd)
Date: Mon, 27 Mar 2023 08:27:51 +0000
Subject: [labnetwork] Strange "sample memory" with LOR 5B
In-Reply-To: <SA1PR01MB6544ED4A152B84375C04F9D1F3849@SA1PR01MB6544.prod.exchangelabs.com>
References: <CALPuYFzLg-QX5tPGX7qShke=8o75W=xVb_NB0tUYquFskr4FRg@mail.gmail.com>
 <QB1PR01MB302553713D9C0CCAA388A3139F849@QB1PR01MB3025.CANPRD01.PROD.OUTLOOK.COM>
 <SA1PR01MB6544ED4A152B84375C04F9D1F3849@SA1PR01MB6544.prod.exchangelabs.com>
Message-ID: <CWLP123MB6543FF7918216F1BA3A45DAAFB8B9@CWLP123MB6543.GBRP123.PROD.OUTLOOK.COM>

Hi All,

We?ve seen ghosting before when using the old Shipley SJR series resist. We replaced those with Megaposit SPR and had the same and have since seen it with Microresist Ma-P. Its happened on both silicon and fused silica (SiO2), though is only visible on a bare substrate when we get condensation on it (eg acetone evaporating or from breath). We tried measuring the surface using white light interferometers and not found anything so generally ignored it. This is using pieces for lithography test exposures, not chemical etching them.

I?d be interested to know where they come from though!

Daniel Lloyd
Development Engineer,
Laser Optical Engineering Ltd.
Building 72a
The Air Cargo Centre
Argosy Road
East Midlands Airport
DE74 2SA
United Kingdom

Tel:               +44 (0) 1332 814612
DD:          +44(0)1332 815112
Mob:            +44( 0)7719285200
web:             www.laseroptical.co.uk<http://www.laseroptical.co.uk/>

Company No 3184967

The Information contained in this E-mail and any subsequent correspondence is private and is intended solely for the intended recipient(s). For those other than the recipient any disclosure, copying, distribution, or any action taken or omitted to be taken in reliance on such information is prohibited and may be unlawful.

From: labnetwork <labnetwork-bounces at mtl.mit.edu> On Behalf Of Hollingshead, Dave
Sent: Friday, March 24, 2023 9:13 PM
To: Gustavo de Oliveira Luiz <deolivei at ualberta.ca>; labnetwork at mtl.mit.edu
Subject: Re: [labnetwork] Strange "sample memory" with LOR 5B

Hi Gustavo,

We?ve seen ghosting before, although as you mention it has usually been caused by mild etching of the substrate in the developer. Based on your comments I wouldn?t count out something else in this case.

This reminds me of some strange behavior we have seen in some of our nLOF processes done on our MLA. We are still trying to investigate what is happening, but we get odd residue or material adhesion issues on reworked samples. One working theory is that the high power density of the MLA laser exposure is either locally heating the resist to the point of excessive cross-linking or somehow modifying the surface during exposure. Microchem has a white paper that seems to lend some credence to this theory (https://www.microchemicals.com/technical_information/exposure_photoresist.pdf, see page 10).

Any chance you have tried (or could try) repeating the process using a contact aligner on the same substrate and see if you still get the same exposure? If it is an MLA-exclusive issue that would be very interested to know and investigate further.

-Dave
Dave Hollingshead
Manager, Research Operations

The Ohio State University
Nanotech West Labs
Suite 100, 1381 Kinnear Rd, Columbus, OH 43212
614.292.1355 Office
hollingshead.19 at osu.edu<mailto:hollingshead.19 at osu.edu> / nanotech.osu.edu<http://nanotech.osu.edu>

Pronouns: he/him/his



From: labnetwork <labnetwork-bounces at mtl.mit.edu<mailto:labnetwork-bounces at mtl.mit.edu>> On Behalf Of Howard Northfield
Sent: Friday, March 24, 2023 14:10
To: Gustavo de Oliveira Luiz <deolivei at ualberta.ca<mailto:deolivei at ualberta.ca>>; labnetwork at mtl.mit.edu<mailto:labnetwork at mtl.mit.edu>
Subject: Re: [labnetwork] Strange "sample memory" with LOR 5B

Yes, previous litho leaves "ghosts", I have seen it often. Howard Northfield Research Associate Advanced Research Complex (ARC) University of Ottawa From: labnetwork <labnetwork-bounces@?mtl.?mit.?edu> on behalf of Gustavo de Oliveira


Yes, previous litho leaves "ghosts", I have seen it often.

Howard Northfield
Research Associate
Advanced Research Complex (ARC)
University of Ottawa
________________________________
From: labnetwork <labnetwork-bounces at mtl.mit.edu<mailto:labnetwork-bounces at mtl.mit.edu>> on behalf of Gustavo de Oliveira Luiz <deolivei at ualberta.ca<mailto:deolivei at ualberta.ca>>
Sent: Friday, March 24, 2023 1:37 PM
To: labnetwork at mtl.mit.edu<mailto:labnetwork at mtl.mit.edu> <labnetwork at mtl.mit.edu<mailto:labnetwork at mtl.mit.edu>>
Subject: [labnetwork] Strange "sample memory" with LOR 5B

Attention : courriel externe | external email
Hello everyone,

While working on a recipe for LOR 5B/AZ 1512 in our automatic development system, I encountered some intriguing effects when reusing wafers for my tests. This could be a problem for our users when developing their own process, so we'd appreciate it if anyone could help us to understand what is going on.

Below is a picture of a sample right before exposure, taken using our MLA150. The dark/bright features you see are NOT etched on the wafer (these wafers were never etched). The marks are from a previous lithography test. They become apparent after coating the sample with LOR 5B and even more after adding AZ 1512. And I don't see them when coating only with AZ 1512 (I reused wafers for that process development without any issues).
[cid:image001.png at 01D9608D.77CE6310]
And what is more intriguing is that these features affect exposure/development of my test mask. For instance, on a virgin sample I can expose and auto-develop with the same recipe (dose and development time) I use for the manual process. On a reused sample, the reisst stack behaves as if it were underexposed (a dose test made this very obvious).

Here are the steps during my tests:

  1.  Piranha clean
  2.  HMDS prime on a YES oven
  3.  Spin-coat with LOR 5B/AZ 1512 (marks show up on a reused sample)
  4.  Expose using either a mask aligner or DWL
  5.  Auto-develop in our Laurell EDC-650 (resist seems underexposed over the marks)

     *   AZ Developer 1:1 ? 90 s
     *   Rinse (DI water) and dry (N2+spin) ? 60-120 s
     *   MF-319 ? 5 s
     *   Rinse (DI water) and dry (N2+spin) ? 60-120 s

  1.  Strip resist with Remover PG
  2.  Repeat all steps for every iteration
At first I thought that this could actually be some etching of my Si wafers by MF-319, even though unlikely given the low TMAH concentration (and I'm not sure why that would affect exposure/development). But the sample in the image above has 2 ?m thermal oxide, so practically impervious to TMAH. Not to mention that the brightest crossing marks come from testing a recipe where TMAH was not used at all. This must be some strange interaction between LOR 5B and the sample surface, which I'd expect to be practically reset after piranha and HMDS priming.

My search for more information regarding LOR 5B and it's sensitivity to surface conditions has proven fruitless so far. And requiring a brand new sample for every iteration can get expensive quite quickly. We'd appreciate it if you could point us to some references where this was discussed in any form, or if you know of a method to avoid this from happening.

I'm sorry for the long email, and thank you in advance for any comments.

Best regards,
--
Gustavo de Oliveira Luiz, PhD
Applications/Research Specialist
nanoFAB, University of Alberta
+1 (780) 619-1463
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From michael.martin at louisville.edu  Mon Mar 27 10:35:32 2023
From: michael.martin at louisville.edu (Martin, Michael)
Date: Mon, 27 Mar 2023 14:35:32 +0000
Subject: [labnetwork] Strange "sample memory" with LOR 5B
In-Reply-To: <CALPuYFzLg-QX5tPGX7qShke=8o75W=xVb_NB0tUYquFskr4FRg@mail.gmail.com>
References: <CALPuYFzLg-QX5tPGX7qShke=8o75W=xVb_NB0tUYquFskr4FRg@mail.gmail.com>
Message-ID: <BN9PR03MB61703E7738C1534670C962F5F28B9@BN9PR03MB6170.namprd03.prod.outlook.com>

Hi Gustavo,
     Like others, we've seen such affects as well. I'm guessing that when you remove the sample from Piranha that a DI water rinse shows uniform sheeting and low contact angle over the entire wafer?  It might be worth trying some oxygen plasma after NMP/ stripper.  We do this often as our NMP bath is reused for quite some time and ends up with several resists solvated in it.  Please share anything else you learn about this!

Regards,
   Michael
________________________________
From: labnetwork <labnetwork-bounces at mtl.mit.edu> on behalf of Gustavo de Oliveira Luiz <deolivei at ualberta.ca>
Sent: Friday, March 24, 2023 1:37 PM
To: labnetwork at mtl.mit.edu <labnetwork at mtl.mit.edu>
Subject: [labnetwork] Strange "sample memory" with LOR 5B

You don't often get email from deolivei at ualberta.ca. Learn why this is important<https://aka.ms/LearnAboutSenderIdentification>

CAUTION: This email originated from outside of our organization. Do not click links, open attachments, or respond unless you recognize the sender's email address and know the contents are safe.

Hello everyone,

While working on a recipe for LOR 5B/AZ 1512 in our automatic development system, I encountered some intriguing effects when reusing wafers for my tests. This could be a problem for our users when developing their own process, so we'd appreciate it if anyone could help us to understand what is going on.

Below is a picture of a sample right before exposure, taken using our MLA150. The dark/bright features you see are NOT etched on the wafer (these wafers were never etched). The marks are from a previous lithography test. They become apparent after coating the sample with LOR 5B and even more after adding AZ 1512. And I don't see them when coating only with AZ 1512 (I reused wafers for that process development without any issues).
[Si_w_Oxide_LOR5b-AZ1512_AsCoated.png]
And what is more intriguing is that these features affect exposure/development of my test mask. For instance, on a virgin sample I can expose and auto-develop with the same recipe (dose and development time) I use for the manual process. On a reused sample, the reisst stack behaves as if it were underexposed (a dose test made this very obvious).

Here are the steps during my tests:

  1.  Piranha clean
  2.  HMDS prime on a YES oven
  3.  Spin-coat with LOR 5B/AZ 1512 (marks show up on a reused sample)
  4.  Expose using either a mask aligner or DWL
  5.  Auto-develop in our Laurell EDC-650 (resist seems underexposed over the marks)
     *   AZ Developer 1:1 ? 90 s
     *   Rinse (DI water) and dry (N2+spin) ? 60-120 s
     *   MF-319 ? 5 s
     *   Rinse (DI water) and dry (N2+spin) ? 60-120 s
  6.  Strip resist with Remover PG
  7.  Repeat all steps for every iteration

At first I thought that this could actually be some etching of my Si wafers by MF-319, even though unlikely given the low TMAH concentration (and I'm not sure why that would affect exposure/development). But the sample in the image above has 2 ?m thermal oxide, so practically impervious to TMAH. Not to mention that the brightest crossing marks come from testing a recipe where TMAH was not used at all. This must be some strange interaction between LOR 5B and the sample surface, which I'd expect to be practically reset after piranha and HMDS priming.

My search for more information regarding LOR 5B and it's sensitivity to surface conditions has proven fruitless so far. And requiring a brand new sample for every iteration can get expensive quite quickly. We'd appreciate it if you could point us to some references where this was discussed in any form, or if you know of a method to avoid this from happening.

I'm sorry for the long email, and thank you in advance for any comments.

Best regards,
--
Gustavo de Oliveira Luiz, PhD
Applications/Research Specialist
nanoFAB, University of Alberta
+1 (780) 619-1463
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From kckeenan at seas.upenn.edu  Mon Mar 27 12:16:49 2023
From: kckeenan at seas.upenn.edu (Kyle Keenan)
Date: Mon, 27 Mar 2023 12:16:49 -0400
Subject: [labnetwork] dispensers for gowning supplies
Message-ID: <CAGTqYdEd7kcQc35y+cd44MSf5NXH3rLmhRdHSEz6nkJsTLQHOw@mail.gmail.com>

Hello, Lab Network Colleagues.

I have been tasked with changing the layout of the gowning room for our
cleanroom, which means I will be changing the way we store and dispense
gowning supplies. Not only do I mean the clean garments themselves, but all
of the disposable items, too. Because of this, I am curious to know how
this is being done at other cleanroom facilities. If you are willing to
describe your setup or, better yet, share some pictures, it would be
greatly appreciated. I would also be interested to know what you do and
don't like about your existing setup.

I look forward to your replies.

Best,
-- 
Kyle Keenan

Senior Manager - Laboratory Operations
Quattrone Nanofabrication Facility
University of Pennsylvania
P: 215-898-7560
F: 215-573-4925
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From kdhemc at rit.edu  Tue Mar 28 17:03:52 2023
From: kdhemc at rit.edu (Karl Hirschman)
Date: Tue, 28 Mar 2023 21:03:52 +0000
Subject: [labnetwork] RIT Student Research Questionnaire
In-Reply-To: <0000000000002f24e605f77093f0@google.com>
References: <0000000000002f24e605f77093f0@google.com>
Message-ID: <PH0PR16MB4735E7E2034D10DCE02CB169C3889@PH0PR16MB4735.namprd16.prod.outlook.com>

Hello Labnetwork,

I would like to request your participation in a survey that will help out a team of students working on a research study of water filtration.   If this is an area that you are familiar with, and your facility usage and requirements, please fill out the questionnaire.  Your help is greatly appreciated!

Karl Hirschman


Dr. Karl D. Hirschman, Micron Professor
Associate Department Head
Electrical and Microelectronic Engineering
Rochester Institute of Technology
168 Lomb Memorial Drive
Rochester, NY  14623-5604
PH: 585-475-5130
kdhemc at rit.edu<mailto:kdhemc at rit.edu>





From: okl9859 at g.rit.edu <okl9859 at g.rit.edu>
Sent: Tuesday, March 21, 2023 6:29 PM
To: kdhemc at g.rit.edu
Subject: RIT Student Research Questionnaire

[Google Forms]


Click on link:

RIT Student Research Questionnaire <https://docs.google.com/forms/d/e/1FAIpQLSenesUobWR7L_hVxxHl85jc5tea7ZqLRIYMVLSumPKS5MC0xA/viewform?vc=0&c=0&w=1&flr=0&usp=mail_form_link>

https://docs.google.com/forms/d/e/1FAIpQLSenesUobWR7L_hVxxHl85jc5tea7ZqLRIYMVLSumPKS5MC0xA/viewform?vc=0&c=0&w=1&flr=0

Hello there! This questionnaire was made by two Rochester Institute of Technology students; Orion Lensing & Benjamin Rippel. We are currently studying water filtration within various industries and how water qualify affects these industries. We have been interviewing many different professionals from water municipalities to agriculture and we now want to look into how water quality affects electronic productions. We are hoping to gain enough information to further our understanding of water filtration/water quality issues so that we may further research possibilities to fix theses problems.

We would greatly appreciate it if you took some time out of your busy days to fill out this questionnaire. It is imperative we collect these responses quickly due to some deadlines (Next Week), please fill these out at the soonest chance you get. Thank you for all your aid and support, we hope you have a wonderful day!

This form was created inside of Rochester Institute of Technology.
Report Abuse<https://docs.google.com/forms/u/1/d/e/1FAIpQLSenesUobWR7L_hVxxHl85jc5tea7ZqLRIYMVLSumPKS5MC0xA/reportabuse?source=https://docs.google.com/forms/d/e/1FAIpQLSenesUobWR7L_hVxxHl85jc5tea7ZqLRIYMVLSumPKS5MC0xA/viewform?sid%3D5cbfef384cb70dee%26vc%3D0%26c%3D0%26w%3D1%26flr%3D0%26token%3D88lwBocBAAA.khgxIMBlob3zhucxSAZDtQ.cv6qsUHuKLwPHT1bofJ5Eg> - Terms of Service<http://www.google.com/accounts/TOS> - Additional Terms<http://www.google.com/google-d-s/terms.html>
Create your own Google Form<https://docs.google.com/forms?usp=mail_form_link>

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From ana.n.cohen.ctr at army.mil  Tue Mar 28 18:40:31 2023
From: ana.n.cohen.ctr at army.mil (Cohen, Ana N CTR USARMY DEVCOM ARL (USA))
Date: Tue, 28 Mar 2023 22:40:31 +0000
Subject: [labnetwork] Strange "sample memory" with LOR 5B
Message-ID: <BN8P111MB1447A051B118966F6CEA4ED99F889@BN8P111MB1447.NAMP111.PROD.OUTLOOK.COM>

Michael got me thinking... Gustavo, could you confirm the DI water rinse
after the piranha looks as you'd expect? I'm not 100% certain the chemistry,
but since HMDS is more a surface treatment than a residue remaining on the
wafer I'm curious if it actually could be unaffected. 

I have definitely seen this 'ghosting' after I solvent strip a patterned
wafer and then need to rinse with DI water. Any water collected on the wafer
surface would match wherever resist had previously been, presumably due to
remaining HMDS. I've not seen it impact further patterning before, but I've
also not used the LOR in my tests and may also have run less tests per
wafer. I'd actually found the following information from EPFL on reworking
HMDS-treated wafers a little while ago when testing out our lab's HMDS
quality (don't know who over there figured this out, but thanks to whoever
did!)
https://www.epfl.ch/research/facilities/cmi/process/photolithography/hmds-ap
plication/  

Either way, the O2 plasma during the cleaning process should be worth a
shot!

--
Ana N. Cohen [she/her/hers]
Photolithography Cleanroom Technician
Contractor | General Technical Services, LLC
US Army Research Laboratory
2800 Powder Mill Road, Adelphi, MD 20783
Tel: 301-394-1527
Email: ana.n.cohen.ctr at army.mil

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From michael.martin at louisville.edu  Wed Mar 29 10:35:25 2023
From: michael.martin at louisville.edu (Martin, Michael)
Date: Wed, 29 Mar 2023 14:35:25 +0000
Subject: [labnetwork] Strange "sample memory" with LOR 5B
In-Reply-To: <BN8P111MB1447A051B118966F6CEA4ED99F889@BN8P111MB1447.NAMP111.PROD.OUTLOOK.COM>
References: <BN8P111MB1447A051B118966F6CEA4ED99F889@BN8P111MB1447.NAMP111.PROD.OUTLOOK.COM>
Message-ID: <BN9PR03MB61700AA90E0720FC2FDDACC0F2899@BN9PR03MB6170.namprd03.prod.outlook.com>

We actually made a TikTok about this subject recently that went somewhat viral.  Despite the off-color humor it seems relevant to the discussion https://www.tiktok.com/@micronanolouisville/video/7214338192995061034  These wafers were cleaned in a 60C NMP bath and it was clear that the HMDS was still on the surface.

________________________________
From: labnetwork <labnetwork-bounces at mtl.mit.edu> on behalf of Cohen, Ana N CTR USARMY DEVCOM ARL (USA) <ana.n.cohen.ctr at army.mil>
Sent: Tuesday, March 28, 2023 6:40 PM
To: labnetwork at mtl.mit.edu <labnetwork at mtl.mit.edu>; Gustavo de Oliveira Luiz <deolivei at ualberta.ca>
Subject: Re: [labnetwork] Strange "sample memory" with LOR 5B

CAUTION: This email originated from outside of our organization. Do not click links, open attachments, or respond unless you recognize the sender's email address and know the contents are safe.

Michael got me thinking... Gustavo, could you confirm the DI water rinse
after the piranha looks as you'd expect? I'm not 100% certain the chemistry,
but since HMDS is more a surface treatment than a residue remaining on the
wafer I'm curious if it actually could be unaffected.

I have definitely seen this 'ghosting' after I solvent strip a patterned
wafer and then need to rinse with DI water. Any water collected on the wafer
surface would match wherever resist had previously been, presumably due to
remaining HMDS. I've not seen it impact further patterning before, but I've
also not used the LOR in my tests and may also have run less tests per
wafer. I'd actually found the following information from EPFL on reworking
HMDS-treated wafers a little while ago when testing out our lab's HMDS
quality (don't know who over there figured this out, but thanks to whoever
did!)
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.epfl.ch%2Fresearch%2Ffacilities%2Fcmi%2Fprocess%2Fphotolithography%2Fhmds-ap&data=05%7C01%7Cmichael.martin%40louisville.EDU%7C1eb5be3d74d4448b451008db301b632d%7Cdd246e4a54344e158ae391ad9797b209%7C0%7C0%7C638156666427001449%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=eTd2IROmftQa49qtYImK3w7CZVOBRwfw2tr9ncJOn%2BI%3D&reserved=0
plication/

Either way, the O2 plasma during the cleaning process should be worth a
shot!

--
Ana N. Cohen [she/her/hers]
Photolithography Cleanroom Technician
Contractor | General Technical Services, LLC
US Army Research Laboratory
2800 Powder Mill Road, Adelphi, MD 20783
Tel: 301-394-1527
Email: ana.n.cohen.ctr at army.mil

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From edward.gonzales at armonicatech.com  Thu Mar 30 16:38:34 2023
From: edward.gonzales at armonicatech.com (edward.gonzales)
Date: Thu, 30 Mar 2023 14:38:34 -0600 (MDT)
Subject: [labnetwork] Anodic Bonding
Message-ID: <627376754.216534.1680208714984@webmail2b.networksolutionsemail.com>

Does anyone have experience with anodic bonding? I have successful bonds with various thickness of SiO2 on Si, 300nm to 1um. The problem is the fluorescence seen duing Raman Spectroscopy. Would anyone know what may cause this?

Thanks,
Edward
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