[labnetwork] Strange "sample memory" with LOR 5B

Gustavo de Oliveira Luiz deolivei at ualberta.ca
Tue May 9 16:13:24 EDT 2023


Hello everyone,

I just wanted to bring an update on this issue of ghosts when reworking
wafers with LOR 5B, as well as give everyone a summary of the information
the community provided since some of the replies seem to have been
addressed to me only.

*TL;DR: To get rid of the ghosts, O2 RIE for 5 min works but a barrel
plasma asher for 20 min does not.*

First the summary and some comments:

   - Some people suggested that developers may indeed etch the substrate
   and cause defects. While this may be true, and I saw that myself, this is
   not such an extensive problem and we don't see this as a problem when
   working on multi-layer projects.
   - Travis Massey brought up the issue of developer residue being trapped
   and not properly rinsed from the undercut region on lift-off masks. Again,
   I don't believe this is the problem, but I do think that this is worth
   paying attention to when developing this kind of recipe. We should think
   about longer rinsing steps to make sure that the developer is completely
   washed away from these harder to reach areas.
   - Dave Hollingshead suggested that local heating from the laser in
   DWL could cause surface modifications. This may be the case, but as my
   update below will show, at least in my case the issue is not irreversible.
   On the other hand, the fact that I also have this issue when using a
   contact aligner tells me that the issue may not be local heating, but it
   may still be some other surface modification due to interaction with light.
   And this must be something related to LOR 5B, since we don't observe this
   on our standard AZ1512 process.
   - A few people suggested that something in the lithography process may
   be changing the reflectivity of the substrate+resist layers. Everything
   points in this direction, however I was not able to determine what is
   causing this. Suggested solutions were O2 plasma (see my update below) and
   deposition of a 20 nm BARC layer before reworking samples.
   - Finally I'd like to address the effect that a few have reported
   regarding the hydrophobicity of the wafer after stripping resist, to which
   there was even a TikTok post about (neat!). We see that behavior after
   stripping the resist from a sample and rinsing it with water. Our
   understanding of this effect is that the exposure and development of the
   photoresist removes HMDS from the substrate, rendering the exposed areas
   hydrophilic while the remaining areas are still hydrophobic as HMDS is
   still there. At least in our case, a 15 min piranha (3:1) cleaning
   procedure is enough to get rid of the remaining HMDS and the whole sample
   becomes hydrophilic again. This is definitely not the cause of the ghosts
   we are observing and, even if HMDS was not completely removed, we apply
   HMDS again as part of the rework and this should make the surface uniform
   again.

I hope I have covered all, or at least most of, the comments I got back.
Now my update:

   - A 5 min O2 RIE step removed whatever it is from the surface of my
   wafers. My procedure was: strip LOR 5B/AZ 1512 with Remover PG (always new,
   so no water or other contamination), piranha clean for 15 min and O2 RIE
   for 5 min (P = 100 mT, RF = 200 W).
   - Since our RIE only supports one sample at a time, I tried doing a
   batch O2 ashing on a barrel plasma system. To our surprise, it did NOT
   work. After 20 min at 250°C, 600 W of RF power and 1.4 Torr, the ghosts
   were still there.

I am sorry for the long message, but I thought that it would be useful to
have a summary of the responses here for anyone looking for information
about this.

Cheers,
--
Gustavo de Oliveira Luiz, PhD
Applications/Research Specialist
nanoFAB, University of Alberta
+1 (780) 619-1463

On Fri, Mar 24, 2023 at 3:57 PM Gustavo de Oliveira Luiz <
deolivei at ualberta.ca> wrote:

> Hi everyone,
>
> First of all, thank you for the comments so far. If anyone else has more
> information or suggestions about this, please keep them coming. I just
> wanted to clarify some things and add a bit more detail on this issue.
>
> Travis Massey mentioned one thing that caught my attention, which was the
> etching at the rims of the mask patterns, where developer may have been
> trapped at after the undercut step with MF-319. Indeed, I observed this
> kind of thing on a Si (no oxide) wafer where I measured up to a few 100 nm
> trenches following the edges of my mask pattern. However this was very
> sparse throughout the wafer, while the marks I've shown cover the whole
> surface and I could not find anything correlating to this large scale
> effect (I used our optical profilometer for this). But interesting that
> liquid being trapped under the overhang of a lift-off mask can cause this,
> which means we need to be more careful with the rinse steps.
>
> Dave Hollingshead suggested the MLA150 laser causing surface
> modifications. Unfortunately I had the same issues when working with a
> contact aligner, so I guess that this is not the case.
>
> Malcom Hathaway suggested a change in the substrate reflectivity, which is
> my current hypothesis. However this seems to affect both Si and oxide,
> since I see this effect on both cases, so this may be in fact a case of
> chemicals sticking to the surface and not coming out even during long
> piranha baths. I have AFM and other surface characterization options
> planned, it is a matter of finding a good time to have it done now.
>
> Thank you all again for the suggestions and references. I'll make sure to
> post an update here if I have anything useful.
>
> Best,
> --
> Gustavo de Oliveira Luiz, PhD
> Applications/Research Specialist
> nanoFAB, University of Alberta
>
> On Fri, Mar 24, 2023 at 3:21 PM Hathaway, Malcolm R <
> hathaway at cns.fas.harvard.edu> wrote:
>
>> Hi Gustavo,
>>
>> Another thought (from a non-photo-expert, for sure!):
>>
>> It may be the prior photo steps are changing the reflectivity of the
>> silicon (or aluminum, on Travis's samples), especially as it shows up as
>> having an effect on dose.  Surface roughening?  A very thin chemical
>> residue?
>>
>> Perhaps an AFM scan would be revealing...
>>
>>
>> Mac Hathaway
>> Harvard CNS
>>
>> ------------------------------
>> *From:* labnetwork <labnetwork-bounces at mtl.mit.edu> on behalf of Massey,
>> Travis <massey21 at llnl.gov>
>> *Sent:* Friday, March 24, 2023 2:30 PM
>> *To:* Gustavo de Oliveira Luiz <deolivei at ualberta.ca>;
>> labnetwork at mtl.mit.edu <labnetwork at mtl.mit.edu>
>> *Subject:* Re: [labnetwork] Strange "sample memory" with LOR 5B
>>
>>
>> Hi Gustavo,
>>
>>
>>
>> I don’t have a definitive answer for you, and I’m certainly no chemist,
>> but also consider the role of AZ Developer (another base) and reactions of
>> NMP with residual water or alkaline solutions.
>>
>>
>>
>> First, the pair of alkaline developers *may* actually be enough to break
>> through the relatively thin oxide created by the piranha, at which point
>> the bases will start attacking the silicon.  Second, if this is only
>> happening with LOR, it’s also possible that residual liquid (likely
>> alkaline) is being trapped under the AZ 1512 then reacting with the NMP.
>> Spinning may not do a great job of removing this liquid trapped beneath the
>> resist overhang.  I suspect a bulk attack, though, since the residual
>> patterns in the wafer reflect the resist pattern itself rather than the
>> perimeters of the resist patterns.  I haven’t noticed this before on SiO2,
>> but NMP alone – and especially water-contaminated NMP – can attack some
>> metals (Al, Cu, etc.).  This paper suggests that acidic or alkaline
>> contaminants in NMP may exacerbate the problem.  I see these ghosts of
>> previous patterns all the time in aluminum-coated wafers I pattern and
>> reuse repeatedly for process development/characterization, and I’ve
>> recently started seeing it on Ti as well – no LOR, just an assortment of
>> positive resists.
>>
>> https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9211805
>> <https://urldefense.proofpoint.com/v2/url?u=https-3A__ieeexplore.ieee.org_stamp_stamp.jsp-3Ftp-3D-26arnumber-3D9211805&d=DwMGaQ&c=WO-RGvefibhHBZq3fL85hQ&r=TEMLD8-VsxCGtcVzmvpT5GFNSczskEKHzW6aYlttmIY&m=1-k7qvkCMYMPtYpozWsK_KGAJGieHTpEbECqW_3lIM8S9M8eXG8-e5DadL6e-7pS&s=Z-bdFigBPa6X1HeTz5-YGnfzpYQPP0zbhVFxbzVW_0A&e=>
>>
>>
>>
>> Best,
>>
>> Travis Massey
>>
>> Center for Micro and Nanotechnology
>>
>> Lawrence Livermore National Laboratory
>>
>>
>>
>> *From:* labnetwork <labnetwork-bounces at mtl.mit.edu> * On Behalf Of *Gustavo
>> de Oliveira Luiz
>> *Sent:* Friday, March 24, 2023 10:37 AM
>> *To:* labnetwork at mtl.mit.edu
>> *Subject:* [labnetwork] Strange "sample memory" with LOR 5B
>>
>>
>>
>> Hello everyone,
>>
>>
>>
>> While working on a recipe for LOR 5B/AZ 1512 in our automatic development
>> system, I encountered some intriguing effects when reusing wafers for my
>> tests. This could be a problem for our users when developing their own
>> process, so we'd appreciate it if anyone could help us to understand what
>> is going on.
>>
>>
>>
>> Below is a picture of a sample right before exposure, taken using our
>> MLA150. The dark/bright features you see are NOT etched on the wafer (these
>> wafers were never etched). The marks are from a previous lithography test.
>> They become apparent after coating the sample with LOR 5B and even more
>> after adding AZ 1512. And I don't see them when coating only with AZ 1512
>> (I reused wafers for that process development without any issues).
>>
>> And what is more intriguing is that these features affect
>> exposure/development of my test mask. For instance, on a virgin sample I
>> can expose and auto-develop with the same recipe (dose and development
>> time) I use for the manual process. On a reused sample, the reisst stack
>> behaves as if it were underexposed (a dose test made this very obvious).
>>
>>
>>
>> Here are the steps during my tests:
>>
>>    1. Piranha clean
>>    2. HMDS prime on a YES oven
>>    3. Spin-coat with LOR 5B/AZ 1512 (marks show up on a reused sample)
>>    4. Expose using either a mask aligner or DWL
>>    5. Auto-develop in our Laurell EDC-650 (resist seems underexposed
>>    over the marks)
>>
>>
>>    1. AZ Developer 1:1 – 90 s
>>       2. Rinse (DI water) and dry (N2+spin) – 60-120 s
>>       3. MF-319 – 5 s
>>       4. Rinse (DI water) and dry (N2+spin) – 60-120 s
>>
>>
>>    1. Strip resist with Remover PG
>>    2. Repeat all steps for every iteration
>>
>> At first I thought that this could actually be some etching of my Si
>> wafers by MF-319, even though unlikely given the low TMAH concentration
>> (and I'm not sure why that would affect exposure/development). But the
>> sample in the image above has 2 μm thermal oxide, so practically impervious
>> to TMAH. Not to mention that the brightest crossing marks come from testing
>> a recipe where TMAH was not used at all. This must be some strange
>> interaction between LOR 5B and the sample surface, which I'd expect to be
>> practically reset after piranha and HMDS priming.
>>
>>
>>
>> My search for more information regarding LOR 5B and it's sensitivity to
>> surface conditions has proven fruitless so far. And requiring a brand new
>> sample for every iteration can get expensive quite quickly. We'd appreciate
>> it if you could point us to some references where this was discussed in any
>> form, or if you know of a method to avoid this from happening.
>>
>>
>>
>> I'm sorry for the long email, and thank you in advance for any comments.
>>
>>
>>
>> Best regards,
>>
>> --
>> Gustavo de Oliveira Luiz, PhD
>> Applications/Research Specialist
>> nanoFAB, University of Alberta
>> +1 (780) 619-1463
>>
>
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