Conference Papers and Presentations

2020

  • M. B. Alawieh, D. Boning and D. Z. Pan, “Wafer Map Defect Patterns Classification using Deep Selective Learning,” accepted to ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, July 19-23, 2020.
  • H. Chen, D. Boning, et al., “Multi-Stage Influence Function,” submitted to International Conference on Machine Learning (ICML), Feb. 2020.

2019

2018

2017

2016

2015

2014

2013

2012

2011

  • K. Balakrishnan, K. Jenkins, and D. Boning, “A Simple Array-Based Test Structure for the AC Variability Characterization of MOSFETs,” IEEE International Symposium on Quality Electronic Design (ISQED), pp. 539-544, March 2011. **
  • A. H. Chang, D. Boning, and H.-S. Lee, “Redundancy in SAR ADCs,” Great Lakes Symposium on Very Large Scale Integration (GLSVLSI), pp. 283-288, Lausanne, Switzerland, May 2011. **
  • K. Balakrishnan, K. A. Jenkins, and D. Boning, “A Ring Oscillator-Based Test Structure for AC Variability Characterization of Individual MOSFETs,” 2nd European Workshop on CMOS Variability (VARI), 4 pages, Grenoble, France, May 2011. ** Best Paper Award, Industry Relevance
  • W. Y. Zhang, K. Balakrishnan, X. Li, D. Boning, and R. Rutenbar, “Toward Efficient Spatial Variation Decomposition via Sparse Regression,” IEEE International Conference on Computer-Aided Design (ICCAD), pp. 162-169, Nov. 2011. **
  • W. Fan, D. Boning, Y. Zhuang, Y. Sampurno, A. Philipossian, M. Moinpour and D. Hooper, “Characterization of CMP Pad Surface Properties and Aging Effects,” International Conference on Planarization Technology (ICPT), Seoul, Korea, Nov. 2011. **
  • J. Johnson, D. Boning, G.-S. Kim, R. Mudhivarthi, P. Safier, and K. Pate, “Slurry Particle Agglomeration Model for Chemical Mechanical Planarization (CMP),” International Conference on Planarization Technology (ICPT), Seoul, Korea, Nov. 2011. **

2010

  • J. O. Diaz, H. K. Taylor, R. J. Shul, R. L. Jarecki, T. M. Bauer, D. S. Boning, and D. L. Hetherington, “A Computationally Simple, Wafer-to-Feature-Level Model of Etch Rate Variation in Deep Reactive Ion Etching,” AVS 57th International Symposium and Exhibition, Albuquerque, NM, Oct. 2010. **
  • D. Boning, A. H. Chang, K. Zuo, J. Wang, and D. Yu, “Test Structures, Circuits, and Extraction Methods for Determining Pattern Density Effects,” IEEE/ACM Workshop on Variability Modeling and Characterization (VMC), San Jose, CA, Nov. 11, 2010. **
  • H. Taylor, K. Simstrup, and D. Boning, “Modeling the Enhancement of Nanoimprint Stamp Bending Compliance by Backside Grooves: Mitigating the Impact of Wafer Nanotopography on Residual Layer Thickness,” 9th International Conference on Nanoimprint and Nanoprint Technology (NNT), Copenhagen, Denmark, Oct. 2010. **
  • D. Boning, A. Kahng, H. Taylor, and Y.-K. Wu, “Chip-Scale Simulation of Residual Layer Thickness Uniformity in Thermal Nanoimprint Lithography: Evaluating Stamp Cavity-Height and ‘Dummy-Fill’ Selection Strategies,” 9th International Conference on Nanoimprint and Nanoprint Technology (NNT), Copenhagen, Denmark, Oct. 2010. **
  • H. Taylor, K. Smistrup, and D. Boning, “Modeling and simulation of stamp deflections in nanoimprint lithography: exploiting backside grooves to enhance residual layer thickness uniformity,” 36th International Conference on Micro & Nano Engineering (MNE2010), Genoa, Sept. 2010. **
  • W. Fan, J. Johnson, and D. S. Boning, “Non-Ohmic Wafer-Level Modeling of Electrochemical-Mechanical Planarization (ECMP),” International Conference on Planarization Technology (ICPT), Phoenix, AZ, Oct. 2010. **
  • Fan, W., J. Johnson, and D. Boning, “Wafer-level Modeling of Electrochemical-Mechanical Planarization (ECMP),” International Conference on Planarization Technology (ICPT), Phoenix, AZ, Oct. 2010. **
  • D. Boning and W. Fan, “Characterization and Modeling of Pad Asperity Response in CMP,” paper E5.4, Chemical-Mechanical Planarization Symposium, MRS Spring Meeting, vol. 1249, pp. 147-154, San Francisco, April 2010. **
  • D. Boning and J. M. Johnson, “Slurry Particle Agglomeration Model for Chemical Mechanical Planarization (CMP),” paper E4.3, Chemical-Mechanical Planarization Symposium, MRS Spring Meeting, vol. 1249, pp. 103-112, San Francisco, April 2010. **
  • D. Boning, “CMP Mechanisms and Models: Progress and Challenges,” Keynote, Symposium V: CMP and Post-CMP Cleaning, China Semiconductor Technology International Conference (CSTIC), Shanghai, China, March 18-19, 2010. **
  • H. Taylor and D. Boning, “Towards nanoimprint lithography-aware layout design checking,” SPIE Advanced Lithography, Design for Manufacturability through Design-Process Integration IV, Proc. of SPIE Vol. 7641, paper 7641-29 (12 pages), San Jose, CA, Feb. 2010. **
  • Anthony, B. W., D. S. Boning, S. F. Yoon, K. Youcef-Toumi, Z. P. Fang, D. Ljubicic, S. Li, I. Reading, V. Shilpiekandula, H. K. Taylor, Z. Xu, and J. Zhao, “Metrology and Process Control for Manufacturing of Microfluidic Devices,” Symposium on Manufacturing of Microfluidic Devices, NTU, Singapore, January 21, 2010. **
  • Fan, W., D. Boning, Y. Zhuang, Y. Sampurno, A. Philipossian, D. Hooper, and M. Moinpour, “Characterization of CMP Pad Surface Properties,” Clarkson Workshop on Chemical-Mechanical Polishing, Lake Placid, NY, Aug. 2010. **

2009

  • H. Taylor and D. Boning, “Fast simulation of pattern dependencies in thermal nanoimprint lithography,” International Conference on Nanoimprint and Nanoprint Technology (NNT), paper C14 (2 pages), San Jose, CA, Nov. 2009. **
  • K. Balakrishnan and D. Boning, “Measurement and Analysis of Contact Plug Resistance Variability,” Custom Integrated Circuits Conference (CICC), pp. 415-422, San Jose, CA, Oct. 2009. **
  • Boning, D., J. Johnson, H. McCulloh, and N. Patel, “The Evolution of Pattern-Density in CMP Modeling,” Symposium E: Science and Technology of Chemical Mechanical Planarization (CMP), Materials Research Society Spring Meeting, San Francisco, CA, April 2009. **

2008

  • H. Taylor, D. S. Boning, C. I. Iliescu, B. Chen, Y.-C. Lam, and X. Chen, “Modeling Pattern Dependencies in the Micro-scale Embossing of Polymeric Layers,” Micro- and Nanotechnology: Materials, Processes, Packaging, and Systems IV, Proc. of SPIE, Vol. 7269, Melbourne, Australia, Dec. 2008. **
  • N. Drego, A. Chandrakasan, and D. Boning, “An All-Digital, Highly Scalable Architecture for Measurement of Spatial Variation in Digital Circuits,” IEEE Asian Solid-State Circuit Conference (ASSCC), Fukuoka, Japan, Nov. 2008. **
  • H. Taylor and D. Boning, “An Integrated Crack-Opening Method for Determining the Work of Fracture of Bonded Polymer Interfaces,” 12th International Conference on Miniaturized Systems for Chemistry and Life Sciences (microTAS 2008), San Diego, CA, Oct. 2008. **
  • H. K. Taylor, Z. Xu, L. Shiguang, K. Youcef-Toumi, S. F. Yoon, and D. S. Boning, “Moire fringe method for the measurement of distortions of hot-embossed polymeric substrates,” to be presented, 9th International Symposium on Laser Metrology, Singapore, June-July 2008. **
  • H. K. Taylor and D. S. Boning, “Diffraction-based Approaches to the In-situ Measurement of Dimensional Variations in Components Produced by Thermoplastic Micro- and Nano-embossing,” 5th International Symposium on Nanomanufacturing, Singapore, Jan. 2008. **
  • Z. G. Xu, S. G. Li, S. F. Yoon, Z. P. Fang, K. Youcef-Toumi, D. J. Burns, V. Shilpiekandula, H. K. Taylor and D. S. Boning, “Complete Surface Distinguishing and Overlapping Technology for Three-dimensional Image Processing of Micro Devices,” 5th International Symposium on Nanomanufacturing, Singapore, Jan. 2008. **
  • A. Philipossian, Y. Sampurno, L. Borucki, Y. Zhuang, S. Misra, K. Holland, and D. Boning, “Characterization of Thermoset and Thermoplastic Polyurethane Pads, and Molded and Non-optimized Machined Grooving Methods for Oxide CMP Applications,” Clarkson Workshop on Chemical-Mechanical Polishing, Lake Placid, NY, Aug. 2008.
  • Boning, D. , K. Balakrishnan, A. Chang, N. Drego, W. Fan, J. Johnson, and H. Taylor, “Measuring and Modeling IC Variability at the Process, Device, and Circuit Levels,” ICCAD Workshop on Test Structure Design for Variability Characterization (TSD), San Jose, CA, Nov. 2008.

2007

2006

  • X. Xie, D. Boning, F. Meyer, and R. Rzehak, “Analysis of Nanotopography and Layout Variations in Patterned STI CMP,” International Conference on Planarization Technology (ICPT), Foster City, CA, Oct. 2006. **
  • Somani, D. Boning, P. Gschwend and R. Reif, “Environmental Impact Evaluation Methodology for Emerging Silicon-Based Technologies,” International Symposium on Electronics and the Environment, San Francisco, May 2006. **
  • Abrokwah, K. O., P. R. Chidambaram, and D. S. Boning, “Pattern Based Prediction for Plasma Etch,” Advanced Semiconductor Manufacturing Conference (ASMC), April 2006. **
  • Xie, X., D. Boning, F. Meyer, R. Rzehak, and P. Wagner, “Analysis and Modeling of Nanotopography Impact in Blanket and Patterned Silicon Wafer Polishing,” Chemical-Me­chanical Planarization for ULSI Multilevel Interconnect Conference (CMP-MIC), Fremont, CA, Feb. 2006.**
  • Xie, X., D. Boning, K. Devriendt, and A. S. Lawing, “Modeling of Friction Evolution During STI CMP as Endpoint Signals,” Chemical-Me­chanical Planarization for ULSI Multilevel Interconnect Conference (CMP-MIC), Fremont, CA, Feb. 2006. **
  • Boning, D. “Variation and Design for Manufacturability in Advanced Fabrication Processes,” keynote address, International Technology Semiconductor Conference – ISTC 2006, Electrochemical Society, Shanghai, China, March 21-23, 2006. **
  • Taylor, H., A. Farahanchi, and D. Boning, “Tool- and pattern-dependent spatial variations in silicon deep reactive ion etch,” International MEMS Conference ’06 (iMEMS), Singapore, May 9-12, 2006. **
  • Xie, X., D. Boning, F. Meyer, R. Rzehak, and P. Wagner, “Analysis and Modeling of Nanotopography Impact in Blanket and Patterned Wafer Polishing,” 5th Silicon Wafer SEMI Standards Workshop, SEMICON Europa 2006, Munich, Germany, April 5, 2006. **

2005

  • Xie, X. and D. Boning, “Relating Friction in CMP to Topography Evolution,” World Tribology Congress III, paper WTC2005-64115, 2 pgs, Washington, D.C., Sept. 2005. **
  • Boning, D. S. and X. Xie, “CMP at the Wafer Edge – Modeling the Interaction Between Wafer Edge Geometry and Polish Performance,” Symposium W: Chemical-Mechanical Planarization – Integration, Technology, and Reliability,” Materials Research Society Spring Meeting, Chemical-Mechanical Planarization – Integration, Technology, and Reliability, MRS Symposium Proceedings vol. 867, pp. 223-234, San Francisco, CA, March 2005. **
  • Sun, H., T. Hill, H. Taylor, M. Schmidt, and D. Boning, “A Two-Level Prediction Model for Deep Reactive Ion Etch (DRIE),” International Conference on Micro Electro Mechanical Systems 2005 (MEMS’05), Miami Beach, FL, Jan. 2005. **
  • Boning, D., “Modeling of Pattern Dependencies in CMP,” Tutorial, Symposium W: Chemical-Mechanical Planarization – Integration, Technology, and Reliability,” Materials Research Society Spring Meeting, San Francisco, CA, March 2005. **
  • Boning, D., L. Pileggi, A. Strojwas, and R. Rutenbar, “Understanding Variation and Its Impact in Devices, Interconnect, and Circuits,” Interconnect Focus Center Workshop, Cambridge, MA, Dec. 2005. **

2004

  • Nassif, S. R., D. Boning, and N. Hakim, “The Care and Feeding of your Statistical Static Timer,” International Conference on Computer Aided Design (ICCAD), San Jose, CA, Nov. 2004. **
  • Xie., X. and D. Boning, “A Comparison of Die-Scale CMP Models,” Recent Advances in Chemical Mechanical Planarization I, Annual Meeting of the American Institute of Chemical Engineers, Austin, TX, Nov. 2004. **
  • Misra, S., Y. Zhuang, Y. Sampurno, E. Hwang, M. Nasrullah, H. Vaidya, M. Deopura, X. Xie, D. Boning, A. Philipossian and P.K. Roy, “Tribological, Thermal, and Kinetic Characterization and Planarity Performance of Novel Pads for ILD CMP Applications,” VLSI Multilevel Interconnect Conference (VMIC), Waikola, HA, Oct. 2004. **
  • Hill, T. F., H. Sun, H. K. Taylor, M. A. Schmidt, and D. S. Boning, “Pattern Density Based Predication for Deep Reactive Ion Etch (DRIE),” Solid-State Sensor, Actuator and Microsystems Workshop, Hilton Head, SC, June 2004. **
  • Cai, H., T. Park, D. Boning, Y. Kang, J. Lee, S. K. Kim, and H. Kim, “Coherent Chip-Scale Modeling for Copper CMP Pattern Dependence,” Paper K2.4, Chemical-Mechanical Polishing Symposium, MRS Spring Meeting, San Francisco, April 2004. **
  • Xie, X., T. Park, D. Boning, A. Smith, P. Allard, and N. Patel, “Characterizing STI CMP Processes with an STI Test Mask Having Realistic Geometric Shapes,” Paper K9.4, Chemical-Mechanical Polishing Symposium, MRS Spring Meeting, San Francisco, April 2004. **
  • Tang, B. and D. Boning, “CMP Modeling and Characterization for Polysilicon MEMS Structures,” Paper K7.6, Chemical-Mechanical Polishing Symposium, MRS Spring Meeting, San Francisco, April 2004. **
  • Boning, D., X. Xie, J. Sorooshian, A. Philipossian, D. Stein, and D. Hetherington, “Relationship Between Patterned Wafer Topography Evolution and STI CMP Motor Current Endpoint Signals,” Chemical-Me­chanical Planarization for ULSI Multilevel Interconnect Conference (CMPMIC), pp. 341-350, Marina Beach, CA, Feb. 2004. **
  • Sorooshian, J., A. Philipossian, L. Borucki, R. Timon, D. Stein, D. Hetherington, and D. Boning, “Impact of Pattern Density on the Effective Pressure During STI CMP,” Chemical-Me­chanical Planarization for ULSI Multilevel Interconnect Conference (CMP-MIC), pp. 358-361, Marina Beach, CA, Feb. 2004. **
  • Sampurno, Y., Y. Zhuang, Z. Li, A. Philipossian, L. Borucki, and D. Boning, “Novel Method for Direct Measurement of Substrate Temperature During Copper CMP,” 9th Annual Clarkson Workshop on Chemical-Mechanical Polishing, Lake Placid, NY, Aug., 2004. **

2003

2002

2001

2000

  • Goodlin, B. E., D. S. Boning, H. H. Sawin, and M. Yang, “Low Open Area Endpoint Detection of Plasma Etching Processes – Limitations and Signal to Noise Characterization,” Sensors and Control in Plasma Processing, American Vacuum Society, Boston, MA, Oct. 2000.**
  • Gower, A., D. Boning, P. Rosenthal, and A. Waldhauer, “Advanced Multi-Objective Control for Epitaxial Silicon Deposition,” Advanced Semiconductor Manufacturing Conference (ASMC), pp. 347-356, Boston, MA, Sept. 2000. **
  • Lee, B, T. Gan, D. Boning, P. Hester, N. Poduje, and W. Baylies, “Nanotopography Effects on Chemical Mechanical Polishing for Shallow Trench Isolation,” Advanced Semiconductor Manu­facturing Conference (ASMC), pp. 425-432, Boston, MA, Sept. 2000. **
  • Goodlin, B. E., D. S. Boning, and H. H. Sawin, “Signal to Noise Characterization for Endpoint De­tection,” Advanced Equipment Control/Advanced Process Control XII Symposium (AEC/APC), Lake Tahoe, NV, Sept. 2000. **
  • Mehrotra, V., S. L. Sam, D. Boning, A. Chandrakasan, R. Valishayee, and S. Nassif, “A Method­ology for Modeling the Effects of Systematic Within-Die Interconnect and Device Variation on Cir­cuit Performance,” Design Automation Conference (DAC), June 2000. **
  • Goodlin, B. E., H. H. Sawin, D. S. Boning, and M. Yang, “Edge Effects and Interferometry in Low Open Area Endpoint Detection of Plasma Etching Processes,” Plasma Processing XIII, Electro­chemical Society Meeting, Toronto, May 2000. **
  • Lee, B., T. Gan, D. S. Boning, J. David, B. A. Bonner, P. McKeever, and T. H. Osterheld, “Using Wafer-Scale Patterns for CMP Analysis,” Materials Research Society Spring Meeting, Paper E8.8/ D11.8, MRS Spring Meeting, San Francisco, CA, April 2000. **
  • White, D., D. Boning, and A. Gower, “Characterization of Endpoint and Wafer-Level Nonuniformity using In-Situ Thermography,” Chemical-Mechanical Planarization for ULSI Multilevel Interconnect Conference (CMP-MIC), pp. 229-236, Santa Clara, CA, March 2000. **
  • Lee, B, D. Hetherington, and D. Boning, “Using Smart Dummy Fill and Selective Reverse Etch­back for Pattern Density Equalization,” Chemical-Mechanical Planarization for ULSI Multilevel Interconnect Conference (CMP-MIC), Santa Clara, CA, March 2000. **
  • Park, T. H, T. Tugbawa, and D. Boning, “Overview of Methods for Characterization of Pattern De­pendencies in Copper CMP,” Chemical-Mechanical Planarization for ULSI Multilevel Interconnect Conference (CMP-MIC), pp. 197-205, Santa Clara, CA, March 2000. **
  • Smith, T., S. J. Fang, G. B. Shinn, J. Stefani, Z. Tang, S. Chang, S. Garza, J. Campbell, and D. Bon­ing, “Improving Within-Die Nonuniformity in Dielectric CMP,” Chemical-Mechanical Planariza­tion for ULSI Multilevel Interconnect Conference (CMP-MIC), pp. 362-364, Santa Clara, CA, March 2000. **
  • Boning, D. S., “Modeling and Simulation Advances in CMP Processes,” Chemical-Mechanical Planarization for ULSI Multilevel Interconnection Short Course, Santa Clara, CA, March 1, 2000.
  • T. Tugbawa, T. Park, and D. Boning, “Framework for Modeling of Pattern Dependencies in Multi-Step Cu CMP Processes,” CMP Symposium, SEMICON West 2000, July, 2000. **
  • B. Lee, D. Boning, W. Baylies, P. Hester, and N. Poduje, “Nanotopography Effects of Chemical Mechanical Polishing on Shallow Trench Isolation,” 5th Annual Clarkson Workshop on Chemical-Mechanical Polishing, Lake Placid, NY, Aug. 2000. **
  • Maag, B., D. Boning, and B. Voelker, “Assessing the Environmental Impact of Copper CMP,” Semiconductor International, Oct. 2000. **
  • Boning, D., B. Lee, W. Baylies, N. Poduje, P. Hester, J. Valley, C. Koliopoulos and D. Hetherington, “Characterization and Modeling of Nanotopography Effects on CMP,” International CMP Symposium 2000, Tokyo, Japan, Dec. 4, 2000. **

1999

  • Park, T., T. Tugbawa, D. Boning, S Hymes, T. Brown, K. Smekalin, and G. Schwartz, “Multi-level Pattern Effects in Copper CMP,” Third International Symposium on Chemical Mechanical Polish­ing in IC Device Manufacturing, 196th Electrochemical Society Meeting, Vol. PV99-37, pp. 94-100, Honolulu, HI, Oct. 1999. **
  • Hymes, S., T. Brown, P. LeFevre, B. Mikkola, R. Bajaj, T. Park, T. Tugbawa, D. Boning, and J. Nguyen, “Modeling of Topography during 1st Step CMP of Cu-Plated Damascene Structures,” Third International Symposium on Chemical Mechanical Polishing in IC Device Manufacturing, 196th Electrochemical Society Meeting, Vol. PV99-37, pp. 149-157, Honolulu, HI, Oct. 1999.
  • Tugbawa, T., T. Park, D. Boning, T. Pan, P. Li, S. Hymes, T. Brown, and L. Camilletti, “A Math­ematical Model of Pattern Dependencies in Copper CMP Processes,” Third International Sympo­sium on Chemical Mechanical Polishing in IC Device Manufacturing, Vol. PV99-37, pp. 605-615, 196th Electrochemical Society Meeting, Honolulu, HI, Oct. 1999. **
  • Smith, T., S. Fang, J. Stefani, G. Shinn, D. Boning and S. Butler, “Device Independent Process Con­trol of Chemical-Mechanical Polishing,” Process Control, Diagnostics, and Modeling in Semicon­ductor Device Manufacturing III, Abstract No. 213, 195th Electrochemical Society Meeting, Seattle, WA, May 1999. **
  • Sawin, H., M. Le, B. Goodlin, D. White, A. Gower, and D. Boning, “Control of Plasma Processes Based on Full Wafer Interferometry and Multivariate Spectral Analysis of Optical Emission Spec­troscopy,” Process Control, Diagnostics, and Modeling in Semiconductor Device Manufacturing III, Abstract No. 232, 195th Electrochemical Society Meeting, Seattle, WA, May 1999. **
  • Smith, T. H., and D. S. Boning, “Process Control in the Semiconductor Industry,” Quality Engi­neering in Semiconductor Manufacturing session, Industrial Engineering Research Conference, Phoenix, AZ, May 22-23, 1999. **
  • Boning, D.S., B. Lee, C. Oji, D. Ouma, T. Park, T. Smith, and T. Tugbawa, “Pattern Depen­dent Modeling for CMP Optimization and Control,” Materials Research Society Spring Meeting, Abstract P5.5, Chemical-Mechanical Polishing – Fundamentals and Challenges, MRS Vol. 566, pp. 197-210, San Francisco, CA, April 1999. **
  • Hymes, S., K. Smekalin, T. Brown, H. Yeung, M. Joffe, M. Banet, T. Park, T. Tugbawa, D. Boning, J. Nguyen, T. West, and W. Sands, “Determination of the Planarization Distance for Copper CMP Process,” Materials Research Society Spring Meeting, Abstract P5.6, MRS Vol. 566, San Fran­cisco, CA, April 1999. **
  • Smith, T. H., D. Boning, S. J. Fang, G. B. Shinn, and J. A. Stefani, “A CMP Model Combining Den­sity and Time Dependencies,” Chemical-Mechanical Planarization for ULSI Multilevel Intercon­nect Conference (CMP-MIC), pp. 97-104, Santa Clara, CA, Feb. 1999. **
  • Park, T., T. Tugbawa, D. Boning, J. Chung, S. Hymes, R. Muralidhar, B. Wilks, K. Smekalin, G. Bersuker, “Electrical Characterization of Copper Chemical Mechanical Polishing,” Chemical-Me­chanical Planarization for ULSI Multilevel Interconnect Conference (CMP-MIC), pp. 184-191, Santa Clara, CA, Feb. 1999. **
  • Fang, S. J., G. B. Shinn, T. H. Smith, and D. Boning, “Advanced Process Control in Dielectric Chemical Mechanical Polishing,” Chemical-Mechanical Planarization for ULSI Multilevel Inter­connect Conference (CMP-MIC), pp. 367-374, Santa Clara, CA, Feb. 1999. **
  • Pan, J. T., P. Li, K. Wijekoon, S. Tsai, F. Redeker, T. Park, T. Tugbawa, and D. Boning, “Copper CMP and Process Control,” Chemical-Mechanical Planarization for ULSI Multilevel Interconnect Conference (CMP-MIC), pp. 423-429, Santa Clara, CA, Feb. 1999. **
  • Chiarello, R., A. Muscat, D. Boning, K. Gleason, S. Karecki, and S. Raghavan, “Multidisciplinary Approaches Target ESH&H,” Solid State Technology, pp. 62-66, Feb. 1999.
  • Boning, D., “A Methodology for Modeling and Characterization of Dielectric CMP Processes,” The CMP Technical Symposium 1999, pp. 23-38, Tokyo, Japan, June 1999.
  • Smith, T., S. Fang, J. Stefani, G. Shinn, S. W. Butler, and D. S. Boning, “Device Independent Run by Run CMP Process Control,” The CMP Technical Symposium 1999, pp. 39-50, Tokyo, Japan, June 1999. **
  • Park, T., T. Tugbawa, D. Boning, and S. Hymes, “Characterization of Pattern Dependent Variation in Copper CMP,” The CMP Technical Symposium 1999, pp. 79-90, Tokyo, Japan, June 1999. **
  • Boning, D., T. Park, T. Tugbawa, S. Hymes, and T. Pan, “Modeling of Copper Chemical Mechanical Polishing,” 4th Annual Clarkson Workshop on Chemical-Mechanical Polishing, Lake Placid, NY, Aug. 1999.
  • Poduje, N., W. Baylies, B. Lee, T. Gan, and D. Boning, “Nanotopology Effects in Chemical Mechanical Polishing,” SEMI-AWG Nanotopography Workshop, Tokyo, Japan, Nov. 29, 1999. **

1998

  • Mehrotra, V., S. Nassif, D. Boning, and J. Chung, “Modeling the Effects of Manufacturing Varia­tion on High-Speed Microprocessor Interconnect Performance,” International Electron Devic­es Meeting (IEDM), pp. 767-770, San Francisco. CA, Dec. 1998. **
  • Smith, T. H., S. J. Fang, J. A. Stefani, G. B. Shinn, D. S. Boning, S. W. Butler, “NOVA In-Line CMP Metrology and Its Use for Lot-to-Lot Process Control,” 45th National Symposium of the American Vacuum Society, Baltimore, MD, Nov. 1998. **
  • White, D. A., B. E. Goodlin, A. Gower, D. Boning, H. Sawin, “Multivariate Spectral Analysis of Optical Emission Spectroscopy for use in Low-Open Area Endpoint Detection,” 45th National Symposium of the American Vacuum Society, Baltimore, MD, Nov. 1998. **
  • Ouma, D., D. Boning, J. Chung, G. Shinn, L. Olsen, and J. Clark, “An Integrated Characterization and Modeling Methodology for CMP Dielectric Planarization,” International Interconnect Technol­ogy Conference (IITC), pp. 67-69, San Francisco, CA, June 1998. **
  • Smith, T., C. Oji, D. Boning, and J. Chung, “Bias and Variance in Multiple Response Surface Mod­eling,” Third International Workshop on Statistical Metrology (IWSM), pp. 60-63, Honolulu, HI, June 1998. **
  • Park, T., T. Tugbawa, J. Yoon, D. Boning, J. Chung, R. Muralidhar, S. Hymes, Y. Gotkis, S. Alam­gir, R. Walesa, L. Shumway, G. Wu, F. Zhang, R. Kistler, and J. Hawkins, “Pattern and Process Dependencies in Copper Damascene Chemical Mechanical Polishing Processes,” VLSI Multilevel Interconnect Conference (VMIC), pp. 437-442, Santa Clara, CA, June 1998. **
  • Pan, J. T., D. Ouma, P. Li, D. Boning, F. Redecker, J. Chung, and J. Whitby, “Planarization and Integration of Shallow Trench Isolation,” VLSI Multilevel Interconnect Conference (VMIC), pp. 467-472, Santa Clara, CA, June 1998. **
  • Boning, D., D. Ouma, and J. Chung, “Extraction of Planarization Length and Response Function in Chemical-Mechanical Polishing,” Materials Research Society 1998 Spring Meeting, Abstract Q5.1, pp. 286-287, San Francisco, CA, May 1998. **
  • Boning, D., and J. Chung, “Statistical Metrology – Measurement and Modeling of Variation for Ad­vanced Process Development and Design Rule Generation,” 1998 International Conference on Characterization and Metrology for ULSI Technology, pp. 395-404, Gaithersburg, MD, March 1998. **
  • Ouma, D., C. Oji, D. Boning, J. Chung, D. Hetherington, and P. Merkle, “Effect of High Relative Speed on Planarization Length in Oxide Chemical Mechanical Polishing,” Chemical-Mechanical Planarization for ULSI Multilevel Interconnect Conference (CMP-MIC), pp. 20-27, Santa Clara, CA, Feb. 1998. ** (postscript | talk-postscript)
  • Park, T., D. Boning, and J. Chung, “Characterization and Modeling of Oxide CMP,” International CMP Technical Symposium for ULSI Multilevel Interconnection, Seoul, Korea, January, 1998. **
  • Boning, D. S., “CMP Pattern Dependent Modeling Developments,” VLSI Multilevel Interconnection State of the Art Seminar, Santa Clara, CA, June 1998.
  • Rosenthal, P. R., P. A. Rosenthal, V. Yakovlev, G. Barna, B. Van Eck, C.M. Nelson, M. L. Spartz, A. Gower, T. Smith, D. Boning, A. Waldhauer, W. Aarts, K. Paul Muller, J. Moyne, J. Mott, R. Mundt, A Perry, A. Weber, R. Bunkofske, “The Next Steps in Advanced Process Control,” Future Fab International, July 1998.
  • Boning, D., “Metrics and Modeling for Pattern-Dependent Planarization Performance,” CMP Technology for ULSI Interconnection, Semicon/West Technical Sessions, San Francisco, CA, July 1998.
  • Chen, H. and D. Boning, “Data-Rich Multivariate Detection/Diagnosis Using Extensions to Principal Components Analysis,” AISE Workshop on Advanced Technologies in Modeling, Scheduling, and Control, Cambridge, MA, July 1998. **
  • Nishimoto, A., T. Smith, D. Ouma, E. Stuckey, and D. Boning, “An In-Situ Sensor for Reduced Consumable Usage Through Control in CMP,” Extended Abstracts, TechCon’98, Semiconductor Research Corporation, Las Vegas, NV, Sept. 1998. **
  • Boning, D., D. Ouma, T. Park, T. Tugbawa, B. Lee, C. Oji, J. Yoon, and T. Smith, “Recent Progress in Pattern Dependent CMP Modeling,” 3rd Annual Clarkson Workshop on Chemical-Mechanical Polishing, Lake Placid, NY, Aug. 16-19, 1998.
  • Ouma, D. O., T. Park, and D. Boning, “MIT CMP Characterization Masks and Applications,” CMP 98 Symposium, Tokyo, Japan, Dec. 1998. **
  • Sachs, E. M., N. M. Patrikalakis, D. Boning, M. J. Cima, T. R. Jackson, and R. Resnick, “The Distributed Design and Fabrication of Metal Parts and Tooling by 3D Printing,Proceedings of the 1998 NSF Design and Manufacturing Grantees Conference, pp. 35-36, Monterrey, Mexico, Jan. 1998.

1997

  • Stine, B. E., V. Mehrotra, D. S. Boning, J. E. Chung, and D. J. Ciplickas, “A Simulation Method­ology for Assessing the Impact of Spatial/Pattern Dependent Variation on Circuit Performance,” In­ternational Electron Devices Meeting (IEDM), pp. 133-136, Wash. DC, Dec. 1997. **
  • Chung, J. E. and D. S. Boning, “CMP ILD Thickness Variation Characterization and Data Analy­sis,” Third International CMP Technical Symposium, Tokyo, Japan, Dec. 1997. **
  • Smith, T. and D. Boning, “Non-Periodic Lot Processing, Random Measurement Delays, and Inter­mittent Lot Processing with an Extended Predictor Corrector Controller,” 44th National Sympo­sium of the American Vacuum Society, San Jose, CA, Oct. 1997. **
  • Le, M., T. Smith, D. Boning, and H. Sawin, “Run-to-Run Process Control and Endpoint Detection on a Dual-Coil TCP with FWI and OES,” 44th National Symposium of the American Vacuum So­ciety, San Jose, CA, Oct. 1997. **
  • Nakagawa, O.S., S.-Y. Oh, F. Eschbach, G. Ray, P. Nikkel, R. Divecha, B. Stine, D. Ouma, D. Bon­ing, and J. Chung, “Modeling of CMP-induced Pattern-dependent ILD Thickness Variation in Mul­tilevel Metallization System,” Advanced Metallization Conference (AMC), San Diego, CA, Oct. 1997. **
  • Maury, A., D. Ouma, D. Boning, and J. Chung, “A Modification to Preston’s Equation and Impact on Pattern Density Effect Modeling,” Advanced Metallization Conference (AMC), San Diego, CA, Oct. 1997. **
  • Ouma, D., B. Stine, R. Divecha, D. Boning, J. Chung, G. Shinn, I. Ali, and J. Clark, “Wafer-Scale Modeling of Pattern Effect in Oxide Chemical Mechanical Polishing,” Manufacturing Yield, Reli­ability, and Failure Analysis session, SPIE 1997 Symposium on Microelectronic Manufacturing, Austin TX, Oct. 1997. **
  • Muthukrishnan, N. M., S. Prasad, B. E. Stine, W. Loh, R. Nagahara, J. E. Chung, D. S. Boning, “Evaluation of pad life in chemical mechanical polishing process using statistical metrology,” Man­ufacturing Yield, Reliability, and Failure Analysis session, SPIE 1997 Symposium on Microelec­tronic Manufacturing, Austin TX, Oct. 1997.
  • Boning, D., “Fundamentals and Applications of Run by Run Process Control,” Tutorial II, Ad­vanced Equipment Control/Advanced Process Control Workshop IX (AEC/APC), SEMATECH, Incline Vil­lage, NV, Sept. 1997.
  • Stefani, J., S. Butler, T. Smith, and D. Boning, “Advanced Process Control of Sputter Depositions”, Advanced Equipment Control/Advanced Process Control Workshop IX (AEC/APC), SEMATECH, Incline Vil­lage, NV, Sept. 1997. **
  • Rosenthal, P., P. Solomon, S. Charpenay, A. Bonanno, W. Zhang, W. Eikleberry, A. Gower, T. Smith, D. Boning, and A. Waldhauer, “Run to Run Control of A Single Wafer Epitaxial Silicon Fabrication Process,” Advanced Equipment Control/Advanced Process Control Workshop IX (AEC/APC), SE­MATECH, Incline Village, NV, Sept. 1997. **
  • Stine, B., D. Boning, J. Chung, D. Ciplickas, and J. Kibarian, “Simulating the Impact of Poly-CD Wafer-Level and Die-Level Variation On Circuit Performance,” Second International Workshop on Statistical Metrology (IWSM), pp. 24 -27, Kyoto, Japan, June 1997. **
  • Stefani, J., S. W. Butler, T. Smith, and D. Boning, “Exponentially Weighted Moving Average-Based Control of Metal Sputter Deposition Processes for Semiconductor Manufacturing,” 4th In­ternational Applied Statistics in Industry Conference, Kansas City, MO, June 1997. **
  • Smith, T., A. Gower, and D. Boning, “A Matrix Math Library for Java,” ACM 1997 Workshop on Java for Science and Engineering Computation, Las Vegas, June 1997. **
  • Le, M., T. Smith, D. Boning, and H. Sawin, “Run-to-Run Process Control on a Dual-Coil Trans­former Coupled Plasma Etcher with Full Wafer Interferometry and Spatially Resolved Optical Emission Spectrometer,” Proc. of the Second International Symposium on Process Control, Diag­nostics, and Modeling in Semiconductor Manufacturing, Electrochemical Society Proc. Vol. 97-9, pp. 3-10, Montreal, May 1997. **
  • Smith, T., D. Boning, J. Stefani, and S. W. Butler, “Run by Run Advanced Process Control of Metal Sputter Deposition,” Proc. of the Second International Symposium on Process Control, Diagnos­tics, and Modeling in Semiconductor Manufacturing, Electrochemical Society Proc. Vol. 97-9, pp. 11-18, Montreal, May 1997. **
  • Boning, D., J. Chung, D. Ouma, and R. Divecha, “Spatial Variation in Semiconductor Processes: Modeling for Control,” Proc. of the Second International Symposium on Process Control, Diagnos­tics, and Modeling in Semiconductor Manufacturing, Electrochemical Society Proc. Vol. 97-9, pp.72-83, Montreal, May 1997. **
  • Stine, B., D. Ouma, R. Divecha, D. Boning, J. Chung, D. L. Hetherington, I. Ali, G. Shinn, J. Clark, O.S. Nakagawa, and S.-Y. Oh, “A Closed-Form Analytic Model for ILD Thickness Variation in CMP Processes,” Chemical-Mechanical Planarization for ULSI Multilevel Interconnect Confer­ence (CMP-MIC), pp. 266-273, Santa Clara, CA, Feb. 1997. **
  • Divecha, R., B. Stine, D. Ouma, J. Yoon, D. Boning, J. Chung, O.S. Nakagawa, and S.-Y. Oh, “Ef­fect of Fine-Line Density and Pitch on Interconnect ILD Thickness Variation in Oxide CMP Pro­cesses,” Chemical-Mechanical Planarization for ULSI Multilevel Interconnect Conference (CMP-MIC), pp. 29-36, Santa Clara, CA, Feb. 1997. ** (text-postscript | figures-postscript)
  • Boning, D. and J. Chung, “Statistical Metrology: Tools for Understanding Variation,” Future Fab International, vol. 1, no. 2, pp. 323-328, Jan. 1997. **
  • Stine, B. E., D. S. Boning, J. E. Chung, and D. Hetherington, “Rapid Characterization and Modeling of Spatial Variation: A CMP Case Study,” Proceedings KLA/Tencor Yield Management Seminar, Semicon/West, San Francisco, CA, July 1997. ** (postscript | slides postscript
  • Boning, D., “Fundamentals and Applications of Run by Run Process Control,” Tutorial II, Advanced Equipment Control/Advanced Process Control Workshop IX (AEC/APC), SEMATECH, Incline Village, NV, Sept. 1997.

1996

1995

  • Chang, E, B. Stine, T. Maung, R. Divecha, D. Boning, J. Chung, K. Chang, G. Ray, D. Bradbury, S. Oh, and D. Bartelink, “Using a Statistical Metrology Framework to Identify Random and Sys­tematic Sources of Intra-Die ILD Thickness Variation for CMP Processes,” International Electron Devices Meeting (IEDM), pp. 499-502, Wash. D.C., Dec. 1995. ** (text postscript) (figures postscript)
  • Boning, D., W. Moyne, T. Smith, J. Moyne, and A. Hurwitz, “Practical Issues in Run by Run Pro­cess Control,” 1995 SEMI/IEEE Advanced Semiconductor Manufacturing Conference and Work­shop (ASMC), pp. 201-208, Cambridge, MA, Nov. 1995. **
  • Boning, D., A. Hurwitz, J. Moyne, W. Moyne, S. Shellman, T. Smith, J. Taylor, and R. Telfeyan, “Run by Run Control of Chemical Mechanical Polishing,” Proc. of IEEE International Electronics Manu­facturing Technology Symposium (IEMT), pp. 81-87, Austin, TX, Oct. 1995. **
  • Boning, D., N. Chaudhry, A. Hurwitz, J. Moyne, W. Moyne, S. Shellman, T. Smith, and R. Telfey­an, “A Multi-level Approach to the Control of a Chemical Mechanical Planarization Process,” 42nd National Symposium of the American Vacuum Society, Abstract #1022, Minneapolis, MN, Oct. 1995. ** (postscript)
  • Wong, K.S. and D. S. Boning, “On In-Situ Etch Rate Estimation from Interferometric Signals,” Proc. of Process Control, Diagnostics, and Modeling in Semiconductor Manufacturing I, 187th Electrochemical Society Meeting, pp. 360-371, Reno, NV, May 1995. ** (postscript)
  • Losleben, P. and D. Boning, “A New Research Paradigm using Internet Collaboration, or Building a National Research Enterprise,” Hierarchical Technology CAD – Process, Device, and Circuits, Stanford University, Stanford, CA, Aug. 1995. **
  • Chang, E, B. Stine, T. Maung, R. Divecha, D. Boning, J. Chung, K. Chang, G. Ray, D. Bradbury, S. Oh, and D. Bartelink, “Using a Statistical Metrology Framework to Identify Random and Systematic Sources of Intra-Die ILD Thickness Variation for CMP Processes,” SEMATECH Statistical Metrology Workshop, Austin TX, August 22, 1995. **

1994

  • Boning, D. S., T. Maung, J. Chung, K.-J. Chang, S.-Y. Oh, and D. Bartelink, “Statistical metrology of interlevel dielectric thickness variation,” Proceedings of the SPIE Symposium on Microelectron­ics Manufacturing, SPIE Vol. 2334, pp. 316-327, Austin, TX, Oct. 1994. **
  • Boning, D. S., J. L. Claman, K. S. Wong, T. J. Dalton, and H. H. Sawin, “Plasma Etch Endpoint via Interferometric Imaging,” Advanced Equipment Control/Advanced Process Control Workshop VI (AEC/APC), SEMATECH, San Antonio, TX, Sept. 1994. **
  • Boning, D. S. and M. B. McIlrath, “Conceptual Graphs and Manufacturing Processes,” Second In­ternational Conference on Conceptual Structures (ICCS), Proceedings Supplement, pp. 1-15, College Park, MD, Aug., 1994.
  • Boning, D. S., J. L. Claman, K. S. Wong, T. J. Dalton, and H. H. Sawin, “Plasma Etch Endpoint via Interferometric Imaging,” Proceedings of the American Control Conference (ACC), pp. 897-911, Balti­more, MD, June 1994. **

1993

1992

  • Boning, D. S., G. Chin, R. Cottle, W. Dietrich, S. Duvall, M. Giles, R. Harris, M. Karasick, N. Kha­lil, M. Law, L. Nackman, S. Nassif, V. T. Rajan, D. Schroeder, R. Tremain, D. Walker, R. Wang, and A. Wong, “Developing and Integrating TCAD Applications with the Semiconductor Wafer Representation,” Workshop on Numerical Modeling of Processes and Devices for Integrated Cir­cuits: NUPAD IV Technical Digest, pp. 199-200, Seattle, WA, May 1992.

1991

1990

1986

  • Boning, D. S., “Wafer Profile Interchange Format,” SRC Workshop on System Architecture for CIM, U.C. Berkeley, November 11-14, 1986.

1985

  • Boning, D. S. and D. A. Antoniadis, “MASTIF – A Workstation Approach to Fabrication Process Design,” International Conference on Computer-Aided Design (IICCAD), pp. 280-282, Santa Clara, Nov., 1985.

** Outgrowth of supervised student research