![]() |
![]() |
|||
| Publications | ||||
3DCSG
Home |
Journal ArticlesS. Das, A. Chandrakasan, and R. Reif. "Calibration of Rent's-Rule Models for Three-Dimensional Integrated Circuits." IEEE Trans. on VLSI Systems, vol. 12, no. 4, pp. 359-366, Apr. 2004. S. M. Alam, D. E. Troxel, and C. V. Thompson, "Layout-specific Circuit Evaluation in Three-dimensional Integrated Circuits," Analog Integrated Circuits and Signal Processing, vol. 35, pp 199-206, May-June 2003. A. Rahman, S. Das, A. Chandrakasan, and R. Reif. "Wiring Requirement and Three-Dimensional Integration Technology for Field Programmable Gate Arrays." IEEE Trans. on VLSI Systems, vol. 11, no. 1, pp. 44-54, Feb. 2003. Conference Publications
Kwon, Y.-S., P. Lajevardi, A. P. Chandrakasan,
F. Honoré, and D. E. Troxel, "A 3-D FPGA Wire
Resource Prediction Model Validated using a 3-D Placement
and Routing Tool," IEEE System-Level Interconnect
Prediction, April 2005. S. Das, A. Chandrakasan, and R. Reif. "Timing, Energy, and Thermal Performance of Three-Dimensional Integrated Circuits." In Proc. GLSVLSI, Apr. 2004. S. Das, A. Chandrakasan, and R. Reif. "Three-Dimensional Integrated Circuits: Performance, Design Methodology, and CAD Tools." In Proc. ISVLSI, Feb. 2003. S. Das, A. Chandrakasan, and R. Reif. "Design Tools for 3-D Integrated Circuits." In Proc. ASP-DAC, pp. 53-56, Jan. 2003. R. Reif, A. Fan, K.-N. Chen, and S. Das. "Fabrication Technologies for Three-Dimensional Integrated Circuits." In Proc. ISQED, pp. 33-37, Mar. 2002. A. Rahman, S. Das, A. Chandrakasan, and R. Reif. "Wiring Requirement and Three-Dimensional Integration of Field-Programmable Gate Arrays." In Proc. ACM/IEEE Intl. Workshop on SLIP, pp. 107-113, Apr. 2001. ThesesShamik Das. "Design Automation and Analysis of Three-Dimensional Integrated Circuits" Ph.D. dissertation, June 2004.
|
|||
| The 3-D Circuits & Systems
Group @ MIT is sponsored by DARPA and MARCO © Massachusetts Institute of Technology Site design by Mara Karapetian |
||||