[labnetwork] RIE through Silicon

[Matthew Moneck]

Hi Long,



The PR approach can work, but we have had problems with wafers coming apart
during the etch and subsequently changing the heat transfer properties.  We
now use 150C heat release tape from Revalpha for bonding of full 4” wafers
or large wafer pieces.  We have been able to achieve up to 7-8hrs of
etching in our STS Multiplex without causing activation of the heat release
surface.  However, the trick is to ensure you apply the tape with no
bubbles.  Subsequent debonding of the wafers can then be done using the
standard release temperature for 150C tape.



Best Regards,

Matt



--

*Matthew T. Moneck, Ph.D*

Executive Director, Claire & John Bertucci Nanotechnology Laboratory

Electrical & Computer Engineering | Carnegie Mellon University

5000 Forbes Avenue, Pittsburgh, PA 15213-3890

Phone:  412-268-5430

ece.cmu.edu <http://www.ece.cmu.edu/>

nanofab.ece.cmu.edu <http://www.nanofab.ece.cmu.edu/>



*From:* labnetwork <labnetwork-bounces at mtl.mit.edu> *On Behalf Of *Chang,
Long
*Sent:* Monday, April 11, 2022 5:10 PM
*To:* labnetwork at mtl.mit.edu
*Subject:* [labnetwork] RIE through Silicon



Hi Guys,



I have an Oxford RIE with backside Helium. I want to etch through the
silicon wafer (380um thick). The largest pattern is a 1mm diameter circle.
My plan is to ride the 4” sample wafer on a 4" carrier wafer with PR. Does
anyone have a good solution to this problem?



Thanks,

Long
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