[labnetwork] Chips on a EVG 620

Wed Feb 17 10:08:41 EST 2016

Hi Jacob,

Like you we have quite a few users who work with small pieces and also use EVG620 aligners. I would guess we see more chip lithography than full wafer lithography. Over the years there have been a couple of techniques developed to deal with this.

1)      The first involves using wide cleanroom tape to cover a 4” (or 2”) vacuum chuck. Small holes are then poked in the vacuum grooves near where the sample needs to be placed. This was the technique of choice for quite some time. Often the vacuum hold is not very good however and overlaps in the tape can cause many issues.

2)      Recently a group of users came up with another option that I personally think works quite well. This involves using a 4” Si wafer as a carrier. Personally I have had success using the unpolished backside of the wafer. A small amount of water is placed on the surface (we use a pipette) to create a very thin film. The sample is then placed on the carrier and the water film adheres the sample to the carrier, keeping it in place during alignment and exposure. It is the same idea as sticking two glass slides together with a drop of water. The key is to limit the amount of water, too much and the sample will simply slide around.

The beauty of this technique is that the sample can be placed anywhere on the carrier. Additionally, the carrier can be marked or scribed to denote the position where the samples need to go for each mask level. The next time the user needs to run the mask they can easily locate where the sample should go. You could go even further and mask and coat a carrier wafer with a grid or location reference for a more exact “fixture”.

With either of the above options the user must still be careful to roughly align the sample on the carrier to ensure that there is enough travel in the stage to do alignment. Dealing with small pieces is never going to be as easy as full wafers but we’ve found that the techniques above do take quite a bit of the pain out of the ordeal.

If you are doing many samples (ie. small production quantities) actual tooling would probably be a better option. For the small, occasional runs that many researchers and students are doing those these are a very low cost and simple way to get reasonable results using small pieces.

If you need any more details please let me know.

Thanks,
-Dave

Dave Hollingshead
Research Engineer
The Ohio State University
Ohio Sensor and Semiconductor Innovation Platform
Nanotech West Lab
Suite 100, 1381 Kinnear Road, Columbus, OH 43212
614.292.1355 Office
hollingshead.19 at osu.edu<mailto:hollingshead.19 at osu.edu> osu.edu<http://osu.edu/>

From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Fouad Karouta
Sent: Tuesday, February 16, 2016 5:25 PM
To: Jacob Trevino; labnetwork at mtl.mit.edu
Subject: Re: [labnetwork] Chips on a EVG 620

Hi Jacob,

Indeed the EVG 620 is not as flexible as the Suss MA6 for instance. We do have an EVG620 and similarly to your case we have people working with small samples and therefore we purchased a mask chuck with a 55mm dia opening allowing user to position the mask to the desired pattern. You need the chuck and the corresponding loading frame. In parallel you also need to have a sample chuck holder for small pieces. We do have one for 2” (EVG said it works for small pieces) but due to the vacuum grooves working with 10x10 mm2 sample will not give you the best resolution as sample cannot be clamped with vacuum. Maybe EVG offers now more suitable chuck for small pieces.
Along all these hardware tools you also need a software upgrade (service visit) to include these parts in the software. A rather expensive upgrade.

Let me know if you need more details on this that we do it outside the labnetowrk.

Kind regards,
Fouad Karouta
ANFF ACT Node Manager

From: labnetwork-bounces at mtl.mit.edu<mailto:labnetwork-bounces at mtl.mit.edu> [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Jacob Trevino
Sent: Wednesday, 17 February 2016 1:06 AM
To: labnetwork at mtl.mit.edu<mailto:labnetwork at mtl.mit.edu>
Subject: [labnetwork] Chips on a EVG 620

Hello All,

At the CUNY ASRC NanoFab, we have a EVG 620 mask aligner with 6” and 4” wafer tooling. We have a number of users who need to process chips of varying sizes. In some cases, users need the flexibility to move the chip across the mask. As I am sure you are familiar, many researchers have several chip layers across one photomask.

It seems as though EVG’s tooling options for chips are fairly limited with less flexibility than I have seen with SUSS chucks in the past. I am curious what other EVG mask aligner owners do to accommodate users who need to perform lithography on chips. Have you made your own custom tooling? Any thoughts would be greatly appreciated.

Best regards,
Jacob

--------------------------------
Jacob Trevino, PhD
NanoFabrication Facility Director
The City University of New York (CUNY)
Advanced Science Research Center (ASRC)
Tel.  (212) 413-3310<tel:%28212%29%20413-3310>
Cel.  (646) 629-1179<tel:%28646%29%20629-1179>
Email: Jacob.Trevino at asrc.cuny.edu<mailto:Jacob.Trevino at asrc.cuny.edu>
Web: http://asrc.cuny.edu/

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