[labnetwork] Chips on a EVG 620

[Mark Giulio Chiappa]

Hi Jacob,

Here at NTNU NanoLab we have a solution. It's not very elegant but it is cheap, flexible and does work. We use low tac tape (I forget the brand but I can let you know if you want it) to cover the entire area of the vacuum chuck with a hole in it for where the user wants to place their chip.  That way the sample is held by system vacuum. The WEC works fine and we've had no complaints about the results.  If your users are really pushing it and have their chip very close to the perimeter of the chuck it may be smart to place a dummy chip or even two to avoid a bad WEC.

We use the same trick with our MA6.

Kind regards
Mark

Sent from my iPhone

On 16 Feb 2016, at 17:41, Jacob Trevino <Jacob.Trevino at asrc.cuny.edu<mailto:Jacob.Trevino at asrc.cuny.edu>> wrote:

Hello All,

At the CUNY ASRC NanoFab, we have a EVG 620 mask aligner with 6" and 4" wafer tooling. We have a number of users who need to process chips of varying sizes. In some cases, users need the flexibility to move the chip across the mask. As I am sure you are familiar, many researchers have several chip layers across one photomask.

It seems as though EVG's tooling options for chips are fairly limited with less flexibility than I have seen with SUSS chucks in the past. I am curious what other EVG mask aligner owners do to accommodate users who need to perform lithography on chips. Have you made your own custom tooling? Any thoughts would be greatly appreciated.

Best regards,
Jacob


--------------------------------
Jacob Trevino, PhD
NanoFabrication Facility Director
The City University of New York (CUNY)
Advanced Science Research Center (ASRC)
Tel.  (212) 413-3310<tel:%28212%29%20413-3310>
Cel.  (646) 629-1179<tel:%28646%29%20629-1179>
Email: Jacob.Trevino at asrc.cuny.edu<mailto:Jacob.Trevino at asrc.cuny.edu>
Web: http://asrc.cuny.edu/


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