[labnetwork] Wafer specification requirement for RIE & DRIE cleaning recopies

[Xuekun Lu]

Dear colleagues,

I am sorry to borrow this thread to ask this question, but it is a related
question. Please let me know if I should start a separate subject.

We have an Oxford PlasmalabSystem 100 with ICP180. Whenever we use a
insulating carrier wafer (fused silica wafer, or silicon wafer coated with
thick SiO2 film), the DC bias reading would be zero. As everybody knows
that this does not mean the sample is subject to zero bias, but in our
case, it seems that the sample DOES subject to zero bias. The etch result
will be more isotropic with very low etch rate. This is even more a problem
when running SiO2 etch with  CHF3/Ar plasma, because this process highly
relies on DC bias (ion bombardment), we got almost no etching when using
insulating carrier wafers. If we use silicon wafer as carrier, everything
would be fine. For other owners of this machine, I am wondering if you have
the same issue or it is just our machine. I had asked Oxford for this, but
had not been able to get an explanation.

Any input would be greatly appreciated!

Thanks,
Xuekun


On Thu, Apr 4, 2019 at 9:58 AM Fabien Dauzou <fabien at edgehogtech.com> wrote:

> Hi Srinivasa,
>
>
>
> In the past we have been using alumina wafer carrier [1-2mm] to proceed
> with cleaning of RIE and DRIE.
>
> You can also use standard wafer with a photoresist or certain coating
> (SiO2, Cr…) to avoid wafer consumption. It should be fine with the helium
> backside cooling.
>
>
>
> Best regards, Bien cordialement,
>
>
>
> Fabien Dauzou (Jr. Eng.)
>
> R&D Process Engineer
>
> fabien at edgehogtech.com
>
> Mob: 438-868-1657
>
> https://www.edgehogtech.com/
>
> 780 Av. Brewster, Montreal, QC, Canada, H4C 2K1
>
> Think green, before printing this email.
>
>
>
>
>
>
>
> *From:* labnetwork-bounces at mtl.mit.edu <labnetwork-bounces at mtl.mit.edu> *On
> Behalf Of *Srinivasa Reddy
> *Sent:* April 4, 2019 1:42 AM
> *To:* labnetwork at mtl.mit.edu
> *Subject:* [labnetwork] Wafer specification requirement for RIE & DRIE
> cleaning recopies
>
>
>
> HI,
>
> I'm Srinivasa Reddy, Manger, Microfabrication Lab, Indian Institute of
> Technology, Madras, Chennai.
>
> This is regarding Wafers specifications for Dummy wafers for RIE & DRIE
> process.
>
> 1. Some times we stick *small prices* to f*ull 4 inch wafer* and do the
> etching process.
>
> Currently we are using *Prime Wafers* ( which costly) and I'm looking to
> replace with Mechanical grade or Test grade wafers.
>
> 2. We also do chamber cleaning runs with the wafers and this also consumes
> significant number of wafers. Here also want to replace the Prime wafer
> with Test or Mechanical grade wafer.
>
>
>
> I've doubt about the Bending/Warping or TTV or backside roughness of the
> wafer and It may lead to higher helium leak rate and process may abort.
>
> Could some one throw light on this issue
>
>
>
>
> Thanks & Regards
>
> Srinivasa Reddy Kuppireddi
>
> Project Manager
>
> Center for NEMS & Nano Photonics (CNNP)
>
> ESB 225, Dept. of Electrical Engineering
>
> Indian Institute of Technology(IIT) Madras
>
> Chennai-600036, Indian
>
> +91 44 2257 5493 (O)
>
> +91 789 326 8010(M)
> _______________________________________________
> labnetwork mailing list
> labnetwork at mtl.mit.edu
> https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork
>


-- 
----------------------------------------
Dr. Xuekun Lu

University of California, San Diego
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